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MarketScreener Homepage  >  Equities  >  Tokyo  >  Denso Corp    6902   JP3551500006

DENSO CORP

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Japan - Patent Issued for Semiconductor Switching Element (USPTO 10,367,091): Denso Corporation

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08/14/2019 | 05:28pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Daily Asia Business -- From Alexandria, Virginia, NewsRx journalists report that a patent by the inventors Saito, Jun (Toyota, Japan); Aoi, Sachiko (Nagakute, Japan); Urakami, Yasushi (Kariya, Japan), filed on December 26, 2016, was published online on August 12, 2019.

The patent’s assignee for patent number 10,367,091 is Denso Corporation (Kariya-shi, Aichi, Japan).

News editors obtained the following quote from the background information supplied by the inventors: “Patent literature 1 discloses a switching element. This switching element includes a semiconductor substrate having a trench provided on its upper surface. An inner surface of the trench is covered by a gate insulation layer. A gate electrode is arranged within the trench. The gate electrode is insulated from the semiconductor substrate by the gate insulation layer. An n-type source region, a p-type body region, an n-type drift region, and a p-type bottom region (p-diffused region) are provided in the semiconductor substrate. The source region is in contact with the gate insulation layer. The body region is in contact with the gate insulation layer on a lower side of the source region. The bottom region is in contact with the gate insulation layer at a bottom surface of the trench. The drift region extends from a position being in contact with a lower surface of the body region to a position being in contact with a lower surface of the bottom region. The drift region is in contact with the gate insulation layer on a lower side of the body region.

“When the switching element of Patent literature 1 turns off, a depletion layer expands from an interface between the body region and the drift region. At this occasion, a depletion layer expands from an interface between the bottom region and the drift region as well. A wide range of the drift region is depleted by these depletion layers.”

As a supplement to the background information on this patent, NewsRx correspondents also obtained the inventors’ summary information for this patent: “As mentioned above, when the switching element of Patent literature 1 turns off, the depletion layer expands from the interface between the bottom region and the drift region into the drift region. Further, this depletion layer expands into the bottom region as well. As a result of this, a potential difference is generated in the depleted semiconductor region between the drift region and the bottom region. At this occasion, due to the gate electrode having a substantially same potential over its entirety, equipotential lines are distributed on a lower side under the trench having the gate electrode accommodated therein, as compared to a region where no trench exists. Due to this, the equipotential lines curve around a corner between the bottom surface of the trench and a side surface thereof. As a result, intervals between the equipotential lines become locally narrow around the corner. Due to this, an electric field concentration occurs around the corner.

“The electric field concentration around an end (that is, the corner) of the trench in a short direction can be alleviated by providing trenches in parallel. Contrary to this, it was difficult to alleviate the electric field concentration around an end (that is, the corner) of the trench in a long direction. Thus, the disclosure herein provides a technique to improve voltage resistance of a switching element by suppressing an electric field concentration around an end of a trench in a long direction.

“The switching element disclosed herein comprises a semiconductor substrate on an upper surface of which a trench is provided; a gate insulation layer covering an inner surface of the trench; and a gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulation layer. The semiconductor substrate comprises a first conductivity type first semiconductor region being in contact with the gate insulation layer; a second conductivity type body region being in contact with the gate insulation layer on a lower side of the first semiconductor region; a second conductivity type bottom region being in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position being in contact with a lower surface of the body region to a position being in contact with a lower surface of the bottom region, being in contact with the gate insulation layer on a lower side of the body region, and separated from the first semiconductor region by the body region. The bottom region comprises a first bottom region being in contact with the gate insulation layer in a first range of the bottom surface that is positioned at an end in a long direction of the trench, and extending from the bottom surface to a first position lower than the bottom surface; and a second bottom region being in contact with the gate insulation layer in a second range of the bottom surface that is adjacent to the first range, and extending from the bottom surface to a second position lower than the first position.

“Notably, one of the first conductivity type and the second conductivity type is an n-type, and the other thereof is a p-type.

“When this switching element turns off, a depletion layer expands from an interface between the body region and the second semiconductor region. Further, a depletion layer expands from an interface between the bottom region and the second semiconductor region (that is, from the lower surface of the bottom region) as well. The second semiconductor region is depleted by these depletion layers. Further, the depletion layer expanding from the interface between the bottom region and the second semiconductor region expands into the bottom region as well. The second bottom region extends to a lower side than the first bottom region (that is, a lower surface of the second bottom region is located on the lower side than a lower surface of the first bottom region). Due to this, an upper end of the depletion layer in the second bottom region comes to be located on the lower side than an upper end of the depletion layer in the first bottom region. Since the electric field is generated in a depleted region, in a depleted range within the second bottom region, equipotential lines are distributed on the lower side than in a depleted range within the first bottom region. Due to this, in the depleted range within the first bottom region, the equipotential lines are distributed in a state where they gradually shift upward from the second bottom region toward the end of the trench in the long direction. As a result, the curve in the equipotential lines around the corner between an end surface (side surface) of the trench in the long direction and the bottom surface of the trench is alleviated. Due to this, intervals between the equipotential lines are suppressed from becoming narrow around the corner, and an electric field concentration around the corner is suppressed. Due to this, this switching element exhibits a high voltage resistance.”

The claims supplied by the inventors are:

“The invention claimed is:

“1. A switching element comprising: a semiconductor substrate on an upper surface of which a trench is provided; a gate insulation layer covering an inner surface of the trench; and a gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulation layer; wherein the semiconductor substrate comprises: a first conductivity type first semiconductor region being in contact with the gate insulation layer; a second conductivity type body region being in contact with the gate insulation layer on a lower side of the first semiconductor region; a second conductivity type bottom region being in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position being in contact with a lower surface of the body region to a position being in contact with a lower surface of the bottom region, being in contact with the gate insulation layer on a lower side of the body region, and separated from the first semiconductor region by the body region; the bottom region comprises: a first bottom region being in contact with the gate insulation layer in a first range of the bottom surface that is positioned at an end in a long direction of the trench, and extending from the bottom surface to a first position lower than the bottom surface; and a second bottom region being in contact with the gate insulation layer in a second range of the bottom surface that is adjacent to the first range, and extending from the bottom surface to a second position lower than the first position.

“2. The switching element according to claim 1, further comprising: an upper electrode provided on the upper surface of the semiconductor substrate and being in contact with the first semiconductor region, wherein the semiconductor substrate further comprises a second conductivity type connection region connecting the bottom region and the upper electrode.

“3. The switching element according to claim 1, wherein the gate insulation layer comprises: a bottom insulation layer covering the bottom surface of the trench, and a side insulation layer covering a side surface of the trench and a thickness of which is thinner than that of the bottom insulation layer.

“4. The switching element according to claim 1, wherein the semiconductor substrate is constituted of silicon carbide, and an effective carrier surface density obtained by integrating an effective carrier density in the second bottom region that is located below the trench in a thickness direction of the semiconductor substrate is greater than 1.4.times.10.sup.13 (cm.sup.-2).

“5. The switching element according to claim 1, wherein the semiconductor substrate is constituted of silicon carbide, and an effective carrier surface density obtained by integrating an effective carrier density in the first bottom region that is located below the trench in a thickness direction of the semiconductor substrate is smaller than 1.4.times.10.sup.13 (cm.sup.-2).

“6. The switching element according to claim 1, wherein the semiconductor substrate is constituted of silicon, and an effective carrier surface density obtained by integrating an effective carrier density in the second bottom region that is located below the trench in a thickness direction of the semiconductor substrate is greater than 2.0.times.10.sup.12 (cm.sup.-2).

“7. The switching element according to claim 1, wherein the semiconductor substrate is constituted of silicon, and an effective carrier surface density obtained by integrating an effective carrier density in the first bottom region that is located below the trench in a thickness direction of the semiconductor substrate is smaller than 2.0.times.10.sup.12 (cm.sup.-2).”

For additional information on this patent, see: Saito, Jun; Aoi, Sachiko; Urakami, Yasushi. Semiconductor Switching Element. U.S. Patent Number 10,367,091, filed December 26, 2016, and published online on August 12, 2019. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=10,367,091.PN.&OS=PN/10,367,091RS=PN/10,367,091

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Daily Asia Business, source Geographic Newsletters

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