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INTEL CORPORATION

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Researchers Submit Patent Application, “Apparatus And Method For Processing An Instruction Matrix Specifying Parallel And Dependent Operations”, for Approval (USPTO 20190227982): Intel Corporation

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08/14/2019 | 05:40pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Computers, Networks & Communications Daily Daily -- From Washington, D.C., NewsRx journalists report that a patent application by the inventor Abdallah, Mohammad A. (Folsom, CA), filed on April 1, 2019, was made available online on July 25, 2019.

The patent’s assignee is Intel Corporation (Santa Clara, California, United States).

News editors obtained the following quote from the background information supplied by the inventors: “The invention relates generally to computer architectures. More particularly, the invention relates to a computer architecture to process matrix instructions specifying parallel and dependent operations.

“Improving computer architecture performance is a difficult task. Improvements have been sought through frequency scaling, Single Instruction Multiple Data (SIMD), Very Long Instruction Word (VLIW), multi-threading and multiple processor techniques. These approaches mainly target improvements in the throughput of program execution. Many of the techniques require software to explicitly unveil parallelism. In contrast, frequency scaling improves both throughput and latency without requiring software explicit annotation of parallelism. Recently, frequency scaling hit a power wall so improvements through frequency scaling are difficult. Thus, it is difficult to increase throughput unless massive explicit software parallelization is expressed.

“In view of the foregoing, it would be desirable to improve computer architecture performance without reliance upon frequency scaling and massive explicit software parallelization.”

As a supplement to the background information on this patent application, NewsRx correspondents also obtained the inventor’s summary information for this patent application: “A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single matrix of instructions specifying parallel and dependent instructions.”

The claims supplied by the inventors are:

“1. An execution unit to execute instructions using a time-lag sliced architecture (TLSA), the execution unit comprising: a first computation unit, wherein the first computation unit includes a plurality of logic slices arranged in order, wherein each of the plurality of logic slices of the first computation unit except a lattermost logic slice is coupled to an immediately following logic slice to provide an output of that logic slice to the immediately following logic slice, wherein the immediately following logic slice is to execute with a time lag with respect to its immediately previous logic slice; and a second computation unit, wherein the second computation unit includes a plurality of logic slices arranged in order, wherein each of the plurality logic slices of the second computation unit except a lattermost logic slice is coupled to an immediately following logic slice to provide an output of that logic slice to the immediately following logic slice, wherein the immediately following logic slice is to execute with a time lag with respect to its immediately previous logic slice, wherein each of the plurality of logic slices of the second computation unit is coupled to a corresponding logic slice of the plurality of logic slices of the first computation unit to receive an output of the corresponding logic slice of the first computation unit.

“2. The execution unit of claim 1, wherein the first computation unit and the second computation unit are configured to access data in a memory in units of data slices with a time lag between data slices.

“3. The execution unit of claim 1, wherein the first computation unit and the second computation unit are configured to execute in a single clock cycle.

“4. The execution unit of claim 1, wherein each logic slice is configured to produce a single digit as its output.

“5. The execution unit of claim 1, wherein logic slices are configured to communicate with other logic slices in an asynchronous manner without the use of synchronous state elements.

“6. The execution unit of claim 1, wherein logic slices are configured to be clocked into state elements, and wherein logic slices are configured to communicate with other logic slices in a synchronous manner using the state elements.

“7. The execution unit of claim 1, wherein logic slices are configured to communicate with other logic slices of the same computation unit in an asynchronous manner without the use of synchronous state elements, and wherein logic slices are configured to be synchronized with corresponding logic slices of a different computation unit using a state element clock.

“8. The execution unit of claim 1, wherein the first computation unit and the second computation unit implement part of a Booth encoded multiplier.

“9. The execution unit of claim 1, wherein the first computation unit and the second computation unit implement part of a left shifter or a right shifter.

“10. A processor to execute instructions using a time-lag sliced architecture (TLSA), the processor comprising: a memory to store data; and an execution unit communicatively coupled to the memory, wherein the execution unit includes a first computation unit and a second computation unit, wherein the first computation unit includes a plurality of logic slices arranged in order, wherein each of the plurality of logic slices of the first computation unit except a lattermost logic slice is coupled to an immediately following logic slice to provide an output of that logic slice to the immediately following logic slice, wherein the immediately following logic slice is to execute with a time lag with respect to its immediately previous logic slice, and wherein the second computation unit includes a plurality of logic slices arranged in order, wherein each of the plurality logic slices of the second computation unit except a lattermost logic slice is coupled to an immediately following logic slice to provide an output of that logic slice to the immediately following logic slice, wherein the immediately following logic slice is to execute with a time lag with respect to its immediately previous logic slice, wherein each of the plurality of logic slices of the second computation unit is coupled to a corresponding logic slice of the plurality of logic slices of the first computation unit to receive an output of the corresponding logic slice of the first computation unit.

“11. The processor of claim 10, wherein the execution unit is configured to access the data stored in the memory in units of data slices with a time lag between data slices.

“12. The processor of claim 10, wherein the first computation unit and the second computation unit are configured to execute in a single clock cycle.

“13. The processor of claim 10, wherein each logic slice is configured to produce a single digit as its output.

“14. The processor of claim 10, wherein logic slices are configured to communicate with other logic slices in an asynchronous manner without the use of synchronous state elements.

“15. The processor of claim 10, wherein logic slices are configured to be clocked into state elements, and wherein logic slices are configured to communicate with other logic slices in a synchronous manner using the state elements.

“16. The processor of claim 10, wherein logic slices are configured to communicate with other logic slices of the same computation unit in an asynchronous manner without the use of synchronous state elements, and wherein logic slices are configured to be synchronized with corresponding logic slices of a different computation unit using a state element clock.

“17. The processor of claim 10, wherein the execution unit implements a Booth encoded multiplier.

“18. The processor of claim 10, wherein the execution unit implements a left shifter or a right shifter.”

For additional information on this patent application, see: Abdallah, Mohammad A. Apparatus And Method For Processing An Instruction Matrix Specifying Parallel And Dependent Operations. Filed April 1, 2019 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190227982%22.PGNR.&OS=DN/20190227982&RS=DN/20190227982

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Computers, Networks & Communications Daily, source Technology Newsletters

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