Log in
E-mail
Password
Remember
Forgot password ?
Become a member for free
Sign up
Sign up
Settings
Settings
Dynamic quotes 
OFFON

MarketScreener Homepage  >  Equities  >  Nyse  >  International Business Machines Corporation    IBM

INTERNATIONAL BUSINESS MACHINES CORPORAT

(IBM)
  Report  
SummaryQuotesChartsNewsRatingsCalendarCompanyFinancialsConsensusRevisions 
News SummaryMost relevantAll newsOfficial PublicationsSector newsAnalyst Recommendations

Patent Application Titled “Vertical Transport Fin Field Effect Transistor With Asymmetric Channel Profile” Published Online (USPTO 20190229200): International Business Machines Corporation

share with twitter share with LinkedIn share with facebook
share via e-mail
0
08/14/2019 | 05:48pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Information Technology Business Daily -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventors Lee, Choonghyun (Rensselaer, NY); Anderson, Brent A. (Jericho, VT); Ok, Injo (Loudonville, NY); Seo, Soon-Cheon (Glenmont, NY), filed on March 22, 2019, was made available online on July 25, 2019.

The assignee for this patent application is International Business Machines Corporation (Armonk, New York, United States).

Reporters obtained the following quote from the background information supplied by the inventors: “Technical Field

“The present invention generally relates to vertical transport fin field effect transistors (VT FinFETs) with varying work function metal layer thicknesses to provide asymmetric channel potential transitions, and more particularly to fabrication of VT FinFETs with different work function metal thicknesses of a gate structure to enhance lateral channel electric fields and increase carrier mobility.

“Description of the Related Art

“A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the device channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the FinFET can be an upright slab of thin rectangular silicon (Si), commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate parallel with the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET can be formed.

“Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.

“With ever decreasing device dimensions, forming the individual components and electrical contacts becomes more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components.”

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventors’ summary information for this patent application: “In accordance with an embodiment of the present invention, a method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate. The method further includes forming an isolation region between the first region and the second region. The method further includes forming a gate dielectric layer on the first vertical fin and the second vertical fin. The method further includes forming a first work function layer on the gate dielectric layer, and removing an upper portion of the first work function layer to expose an upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region. The method further includes forming a second work function layer on a remaining portion of the first work function layer and the exposed upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region, wherein the remaining portion of the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

“In accordance with another embodiment of the present invention, a plurality of vertical fin field effect transistors is provided. The plurality of vertical fin field effect transistors include a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, and an isolation region between the first region and the second region. The plurality of vertical fin field effect transistors further include a gate dielectric layer on the first vertical fin and the second vertical fin, a first combined work function layer on a lower portion of the gate dielectric layer on the second vertical fin, and a second work function layer on an upper portion of the gate dielectric layer on the second vertical fin. The plurality of vertical fin field effect transistors further include a second combined work function layer on a lower portion of the gate dielectric layer on the first vertical fin, and a fourth work function layer on an upper portion of the gate dielectric layer on the first vertical fin.

“In accordance with yet another embodiment of the present invention, a plurality of vertical fin field effect transistors is provided. The plurality of vertical fin field effect transistors include a first bottom source/drain region on a first region of a substrate and a second bottom source/drain region on a second region of the substrate with an isolation region between the first region and the second region. The plurality of vertical fin field effect transistors further include a first vertical fin on the first region of the substrate and a second vertical fin on the second region of the substrate, and a gate dielectric layer on the first vertical fin and the second vertical fin. The plurality of vertical fin field effect transistors further include a first combined work function layer on a lower portion of the gate dielectric layer on the second vertical fin, and a second work function layer on an upper portion of the gate dielectric layer on the second vertical fin. The plurality of vertical fin field effect transistors further include a second combined work function layer on a lower portion of the gate dielectric layer on the first vertical fin, and a fourth work function layer on an upper portion of the gate dielectric layer on the first vertical fin.

“These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.”

The claims supplied by the inventors are:

“1. A method of forming a plurality of vertical fin field effect transistors, comprising: forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate; forming an isolation region between the first region and the second region; forming a gate dielectric layer on the first vertical fin and the second vertical fin; forming a first work function layer on the gate dielectric layer; removing an upper portion of the first work function layer to expose an upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region; and forming a second work function layer on a remaining portion of the first work function layer and the exposed upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region, wherein the remaining portion of the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

“2. The method of claim 1, further comprising removing all of the first work function layer and second work function layer to expose the gate dielectric layer on the first vertical fin on the first region.

“3. The method of claim 2, further comprising forming a third work function layer on the gate dielectric layer on the first vertical fin on the first region and the second work function layer and first combined work function layer on the second vertical fin on the second region.

“4. The method of claim 3, further comprising removing an upper portion of the third work function layer to expose an upper portion of the gate dielectric layer on the first vertical fin in the first region.

“5. The method of claim 4, further comprising forming a fourth work function layer on the upper portion of the gate dielectric layer on the first vertical fin in the first region and the remaining portion of the third work function layer, wherein the remaining portion of the third work function layer and fourth work function layer forms a second combined work function layer with a step in the fourth work function layer.

“6. The method of claim 5, wherein the first and second work function layers are a different work function material from the third and fourth work function layers.

“7. The method of claim 6, wherein the first and second work function layers each have a thickness in the range of about 1 nm to about 10 nm.

“8. The method of claim 7, wherein the third and fourth work function layers each have a thickness in the range of about 1 nm to about 10 nm.

“9. The method of claim 8, wherein the first and second work function layers are selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), and ruthenium (Ru).

“10. The method of claim 8, wherein the third and fourth work function layers are selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN), lanthanum (La) doped TiN, and lanthanum (La) doped TaN.

“11. A method of forming a plurality of vertical fin field effect transistors, comprising: forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate; forming an isolation region between the first region and the second region; forming a gate dielectric layer on the first vertical fin and the second vertical fin; forming a first combined work function layer on a lower portion of the gate dielectric layer on the second vertical fin; forming a second work function layer on an upper portion of the gate dielectric layer on the second vertical fin; forming a second combined work function layer on a lower portion of the gate dielectric layer on the first vertical fin; and forming a fourth work function layer on an upper portion of the gate dielectric layer on the first vertical fin.

“12. The method of claim 11, further comprising forming a first bottom source/drain region on the first region of the substrate and a second bottom source/drain region on the second region of the substrate, wherein the first bottom source/drain region is doped with an n-type dopant, and the second bottom source/drain region is doped with a p-type dopant.

“13. The method of claim 12, wherein the fourth work function layer has a thickness in the range of about 1 nm to about 10 nm.

“14. The method of claim 13, wherein the second work function layer has a thickness in the range of about 1 nm to about 10 nm.

“15. The method of claim 14, wherein the second work function layer is a different work function material from the fourth work function layer.

“16. A method of forming a plurality of vertical fin field effect transistors, comprising: forming a first bottom source/drain region on the first region of the substrate and a second bottom source/drain region on the second region of the substrate, wherein the first bottom source/drain region is doped with an n-type dopant, and the second bottom source/drain region is doped with a p-type dopant; forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate; forming an isolation region between the first region and the second region; forming a gate dielectric layer on the first vertical fin and the second vertical fin; forming a first work function layer on the gate dielectric layer; forming a cover layer on the first work function layer, wherein the cover layer covers a lower portion of the first work function layer; removing an upper portion of the first work function layer to expose an upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region; and removing the cover layer.

“17. The method of claim 16, further comprising forming a second work function layer on a remaining portion of the first work function layer and the exposed upper portion of the gate dielectric layer on the first vertical fin on the first region and the second vertical fin on the second region, wherein the remaining portion of the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

“18. The method claim 17, wherein the first and second work function layers are a material selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN), lanthanum (La) doped TiN, and lanthanum (La) doped TaN.

“19. The method of claim 17, wherein the first work function layer and the second work function layer each have a thickness in the range of about 1 nm to about 10 nm.

“20. The method of claim 19, further comprising removing the first combined work function layer from the first vertical fin.”

For more information, see this patent application: Lee, Choonghyun; Anderson, Brent A.; Ok, Injo; Seo, Soon-Cheon. Vertical Transport Fin Field Effect Transistor With Asymmetric Channel Profile. Filed March 22, 2019 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190229200%22.PGNR.&OS=DN/20190229200&RS=DN/20190229200

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Information Technology Business Daily, source Technology Newsletters

share with twitter share with LinkedIn share with facebook
share via e-mail
0
Latest news on INTERNATIONAL BUSINESS MAC
09:59aINTERNATIONAL BUSINESS MACHINES : IHL Group Names IBM Order Management as a Lead..
PR
08/16INTERNATIONAL BUSINESS MACHINES : IBM looking for more opportunities for transfo..
AQ
08/152022 Business Analytics & Enterprise Software Market Growth, Forecasts and Ke..
AQ
08/14INTERNATIONAL BUSINESS MACHINES : IBM looking for more opportunities for transfo..
AQ
08/14Stocks: Dividends in Spotlight as Bond Yields Drop -- WSJ
DJ
08/12INTERNATIONAL BUSINESS MACHINES : IBM files patent for blockchain web browser
AQ
08/12INTERNATIONAL BUSINESS MACHINES : Frost and Sullivan-Automated Software Testing ..
AQ
08/08INTERNATIONAL BUSINESS MACHINES : ISM Canada Appoints Hasnain Versi as New Presi..
AQ
08/08INTERNATIONAL BUSINESS MACHINES CORP : Ex-dividend day for
FA
08/07NEWS HIGHLIGHTS : Top Company News of the Day
DJ
More news
Financials (USD)
Sales 2019 77 842 M
EBIT 2019 12 712 M
Net income 2019 10 433 M
Debt 2019 39 695 M
Yield 2019 4,75%
P/E ratio 2019 11,7x
P/E ratio 2020 10,9x
EV / Sales2019 2,05x
EV / Sales2020 1,89x
Capitalization 120 B
Chart INTERNATIONAL BUSINESS MACHINES CORPORATION
Duration : Period :
International Business Machines Corporation Technical Analysis Chart | MarketScreener
Full-screen chart
Technical analysis trends INTERNATIONAL BUSINESS MAC
Short TermMid-TermLong Term
TrendsBearishNeutralBullish
Income Statement Evolution
Consensus
Sell
Buy
Mean consensus HOLD
Number of Analysts 23
Average target price 155,47  $
Last Close Price 135,04  $
Spread / Highest target 29,6%
Spread / Average Target 15,1%
Spread / Lowest Target -11,1%
EPS Revisions
Managers
NameTitle
Virginia M. Rometty Chairman, President & Chief Executive Officer
James J. Kavanaugh Chief Financial Officer & Senior Vice President
John E. Kelly Senior VP-Cognitive Solutions & Research
Martin Jetter SVP-Global Technology Services
Sidney Taurel Independent Director
Sector and Competitors
1st jan.Capitalization (M$)
INTERNATIONAL BUSINESS MACHINES CORPORATION18.80%119 629
ACCENTURE38.42%124 357
TATA CONSULTANCY SERVICES14.37%113 467
AUTOMATIC DATA PROCESSING28.86%73 319
VMWARE, INC.5.14%59 000
INFOSYS LTD17.54%46 111