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MarketScreener Homepage  >  Equities  >  Tokyo  >  Renesas Electronics Corporation    6723   JP3164720009

RENESAS ELECTRONICS CORPORATION

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“Manufacturing Method Of Semiconductor Device” in Patent Application Approval Process (USPTO 20190228987): Renesas Electronics Corporation

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08/14/2019 | 05:47pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Japan Daily Report -- A patent application by the inventor TANIGUCHI, Kei (Tokyo, Japan), filed on April 18, 2018, was made available online on July 25, 2019, according to news reporting originating from Washington, D.C., by NewsRx correspondents.

This patent application is assigned to Renesas Electronics Corporation (Tokyo, Japan).

The following quote was obtained by the news editors from the background information supplied by the inventors: “Japanese Unexamined Patent Application Publication No. 2014-7363 (Patent Document 1) describes a technique of forming a single ditch on a lower surface of a die pad exposed from a sealing body.

“Japanese Unexamined Patent Application Publication No.

“2012-94598 (Patent Document 2) describes a technique of removing resin burrs formed on a die pad exposed from a sealing body.”

In addition to the background information obtained for this patent application, NewsRx journalists also obtained the inventor’s summary information for this patent application: “Problems to be Solved by the Invention

“As a package configuration of a semiconductor device, there is a tab exposure type semiconductor device in which a lower surface of a chip mounting portion (die pad, tab) on which a semiconductor chip is mounted is exposed from a sealing body. This tab exposure type semiconductor device has the advantage that heat generated in the semiconductor chip can be efficiently radiated from the lower surface of the die pad exposed from the sealing body.

“However, the manufacturing process of the tab exposure type semiconductor device includes a process of forming the sealing body while exposing the lower surface of the chip mounting portion, and the resin constituting the sealing body inevitably leaks out on the lower surface of the chip mounting portion in the actual process of forming the sealing body. When this resin leakage increases, the region covered with the resin in the lower surface of the chip mounting portion becomes larger, and there is a possibility that the heat radiation efficiency from the exposed chip mounting portion decreases. Namely, even if the chip mounting portion is designed so that the lower surface thereof is exposed, since the resin leakage inevitably occurs in the actual manufacturing process, how the resin leakage onto the lower surface of the chip mounting portion can be suppressed becomes important from the viewpoint of improving the heat radiation efficiency of the semiconductor device. In other words, in order to manufacture a semiconductor device in which the lower surface of the chip mounting portion is exposed to improve heat radiation efficiency, it is necessary to suppress the increase in the resin leakage that inevitably occurs in the actual manufacturing process.

“Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

“Means for Solving the Problems

“In a manufacturing method of a semiconductor device in one embodiment, when resin enters a first ditch formed on a lower surface of a chip mounting portion by a process of forming a sealing body made of the resin, the resin embedded in the first ditch is removed by a process of cleaning the lower surface of the chip mounting portion, and a plating film is formed also on an inner wall of the first ditch in a process of forming the plating film on the lower surface of the chip mounting portion.

“Effects of the Invention

“According to one embodiment, the reliability of the semiconductor device can be improved.”

The claims supplied by the inventors are:

“1. A semiconductor device comprising: a chip mounting portion having a lower surface on which a first ditch is formed; a semiconductor chip mounted on an upper surface of the chip mounting portion; a lead electrically connected to a pad of the semiconductor chip through a conductive member; and a sealing body configured to seal the semiconductor chip, wherein the lower surface of the chip mounting portion is exposed from the sealing body, and wherein a plating film is formed on the lower surface including an inside of the first ditch.

“2. The semiconductor device according to claim 1, wherein resin constituting the sealing body is not formed inside the first ditch.

“3. The semiconductor device according to claim 1, wherein the first ditch is formed along an outer peripheral portion of the chip mounting portion.

“4. The semiconductor device according to claim 1, wherein a depth of the first ditch is 1/2 or less of a thickness of the chip mounting portion.

“5. The semiconductor device according to claim 1, wherein the first ditch has a V-shaped cross section.

“6. The semiconductor device according to claim 1, wherein a second ditch is further formed on the lower surface of the chip mounting portion so as to be spaced apart from the first ditch.

“7. The semiconductor device according to claim 6, wherein the second ditch is formed on an inner side of the chip mounting portion relative to the first ditch.

“8. The semiconductor device according to claim 6, wherein a depth of the first ditch and a depth of the second ditch are both 1/2 or less of a thickness of the chip mounting portion.

“9. The semiconductor device according to claim 7, wherein a depth of the first ditch is deeper than a depth of the second ditch.

“10. The semiconductor device according to claim 6, wherein the plating film is formed also on an inner wall of the second ditch.

“11. The semiconductor device according to claim 6, wherein resin constituting the sealing body is not formed inside the second ditch.

“12. The semiconductor device according to claim 1, wherein a step portion spaced apart from the first ditch is formed at an outer end of the lower surface of the chip mounting portion.

“13. The semiconductor device according to claim 12, wherein the first ditch is formed on an inner side of the step portion.

“14. The semiconductor device according to claim 12, wherein a depth of the first ditch is shallower than a difference in level of the step portion.

“15. The semiconductor device according to claim 12, wherein a second ditch is formed on an inner side of the first ditch on the lower surface of the chip mounting portion, and a distance between the step portion and a center position of the first ditch is smaller than a distance between the center position of the first ditch and a center position of the second ditch in a cross-sectional view.

“16. The semiconductor device according to claim 12, wherein resin constituting the sealing body is formed inside the step portion.

“17. The semiconductor device according to claim 1, wherein the chip mounting portion has a first side extending in a first direction, a second side crossing the first side, and a corner portion which is an intersection of the first side and the second side, wherein the first ditch includes a first portion parallel to the first side, a second portion parallel to the second side, and a third portion connecting the first portion and the second portion, and wherein a distance between the third portion of the first ditch and the corner portion is longer than a distance between the first portion of the first ditch and the first side, and is longer than a distance between the second portion of the first ditch and the second side.

“18. The semiconductor device according to claim 17, wherein an angle formed by the third portion and the first portion is an obtuse angle, and wherein an angle formed by the third portion and the second portion is an obtuse angle.”

URL and more information on this patent application, see: TANIGUCHI, Kei. Manufacturing Method Of Semiconductor Device. Filed April 18, 2018 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190228987%22.PGNR.&OS=DN/20190228987&RS=DN/20190228987

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Japan Daily Report, source Geographic Newsletters

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Financials (JPY)
Sales 2019 737 B
EBIT 2019 39 746 M
Net income 2019 19 764 M
Debt 2019 660 B
Yield 2019 -
P/E ratio 2019 52,8x
P/E ratio 2020 17,8x
EV / Sales2019 2,37x
EV / Sales2020 2,03x
Capitalization 1 085 B
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Number of Analysts 14
Average target price 712,86  JPY
Last Close Price 637,00  JPY
Spread / Highest target 101%
Spread / Average Target 11,9%
Spread / Lowest Target -21,5%
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Bunsei Kure President, CEO & Representative Director
Tetsuya Tsurumaru Chairman
Hidetoshi Shibata CFO, Director & Managing Executive Officer
Tetsuro Toyoda Independent Non-Executive Outside Director
Jiro Iwasaki Independent Non-Executive Outside Director
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