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MarketScreener Homepage  >  Equities  >  KOREA EXCHANGE  >  Samsung Electronics Co Ltd    005930   KR7005930003

SAMSUNG ELECTRONICS CO LTD

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Patent Application Titled “Semiconductor Devices” Published Online (USPTO 20190229121): Samsung Electronics Co. Ltd.

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08/14/2019 | 05:47pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at South Korea Daily Report -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventors Kim, Sangyoung (Yangpyeong-gun, South Korea); LEE, Hyung Jong (Osan-si, South Korea); BAE, Deokhan (Hwaseong-si, South Korea), filed on April 3, 2019, was made available online on July 25, 2019.

The assignee for this patent application is Samsung Electronics Co. Ltd. (Suwon-si, South Korea).

Reporters obtained the following quote from the background information supplied by the inventors: “The present inventive concept relates to semiconductor devices, and, more particularly, to semiconductor devices including an SRAM cell.

“Semiconductor devices are widely used in the electronic industry due to their compact size, multifunction, and/or low manufacturing cost. The semiconductor devices may include, on at least portions thereof, memory cells that store logic data.

“The memory cells may include nonvolatile memory cells and volatile memory cells. A nonvolatile memory cell is characterized by the ability to retain its stored data even when its power supply is interrupted. For example, a flash memory cell, a phase change memory cell, and a magnetic memory cell are all examples of nonvolatile memory cells. A volatile memory cell is characterized by losing its stored data when its power supply is interrupted. For example, a static random access memory (SRAM) cell and a dynamic random access memory (DRAM) cell are all examples of volatile memory cells. An SRAM cell typically has low power consumption and high operating speed in comparison with a DRAM cell.

“An SRAM cell may be configured with a node contact between adjacent gate structures. Typically, the node contact is spaced apart from the adjacent gate structures at approximately the same distance. The node contact is generally only designed to be electrically connected to one of the two adjacent gate structures. In highly integrated memory devices, however, the margins between the node contact and the adjacent gate structures may be small, which may increase the risk of electrical shorts between the node contact and an adjacent gate structure.”

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventors’ summary information for this patent application: “Embodiments of the present inventive concept provide a semiconductor device optimized for high integration.

“Embodiments of the present inventive concept provide a semiconductor device having improved electrical characteristics.

“According to exemplary embodiments of the present inventive concept, a semiconductor device may comprise: a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction; a first gate structure that extends across the first and second active patterns; a second gate structure that is spaced apart from the first gate structure; and a node contact between the first gate structure and the second gate structure that electrically connects the first active pattern and the second active pattern to each other. The node contact may comprise a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact may be shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

“According to exemplary embodiments of the present inventive concept, a semiconductor device may comprise: a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction; a first gate structure that extends across the first and second active patterns; and a node contact on a side of the first gate structure and electrically connects the first and second active patterns to each other. The node contact may comprise a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The first end of the node contact may be spaced apart from the first gate structure at a first distance. The second end of the node contact may be spaced apart from the first gate structure at a second distance greater than the first distance.

“According to exemplary embodiments of the present inventive concept, a semiconductor device may comprise: a first gate structure on a substrate; a second gate structure spaced apart in a first direction from the first gate structure; a third gate structure spaced apart in the first direction from the first gate structure; and a node contact between the first gate structure and the second gate structure and between the first gate structure and the third gate structure. The second and third gate structures may be aligned with each other in a second direction crossing the first direction. The node contact may comprise a first end between the first and third gate structures and a second end between the first and second gate structures. The second end of the node contact may be shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

“It is noted that aspects of the inventive concepts described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other aspects of the inventive concepts are described in detail in the specification set forth below.”

The claims supplied by the inventors are:

“1. A semiconductor device, comprising: a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, each of the first active pattern and the second active pattern having an active fin protruding upwardly; a first gate structure that extends across the first active pattern and the second active pattern and covers top and side surfaces of the active fin of each of the first active pattern and the second active pattern; a second gate structure that is spaced apart from the first gate structure; and a node contact between the first gate structure and the second gate structure, wherein the node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern, the first end of the node contact being connected to a source/drain region on the first active pattern, the second end of the node contact being connected to a gate electrode of the second gate structure, the second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

“2. The semiconductor device of claim 1, wherein the first end of the node contact is spaced apart from the first gate structure at a first distance, the second end of the node contact being spaced apart from the first gate structure at a second distance greater than the first distance.

“3. The semiconductor device of claim 2, wherein the second end of the node contact is spaced apart from the second gate structure at a third distance less than the first and second distances.

“4. The semiconductor device of claim 2, further comprising a third gate structure that is spaced apart from the first gate structure across the node contact and extends across the first active pattern, wherein the second gate structure and the third gate structure are arranged to be spaced apart from each other in the second direction, wherein the second end of the node contact is spaced apart from the second gate structure at a third distance, and the first end of the node contact is spaced apart from the third gate structure at a fourth distance different from the third distance.

“5. The semiconductor device of claim 4, wherein the third distance is less than the fourth distance.

“6. The semiconductor device of claim 1, wherein the second end of the node contact includes a portion of the node contact, which is connected to a source/drain region on the second active pattern, and a gate contact connected to a top surface of the gate electrode of the second gate structure.

“7. The semiconductor device of claim 6, wherein the gate electrode of the second gate structure is electrically connected to the source/drain regions of the first and second active patterns through the node contact.

“8. The semiconductor device of claim 6, wherein the gate contact comprises a same material as that of the node contact.

“9. The semiconductor device of claim 6, wherein the gate contact has a top surface at a same height as that of a top surface of the node contact relative to the substrate.

“10. The semiconductor device of claim 1, wherein the first active pattern and the second active pattern have different conductivity types from each other.

“11. A semiconductor device, comprising: a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, each of the first active pattern and the second active pattern having an active fin protruding upwardly; a first gate structure and a second gate structure that extend in the second direction on the substrate and are spaced apart from each other in the first direction, the first gate structure crossing the first and second active patterns and covering top and side surfaces of the active fin of each of the first and second active patterns; and a node contact between the first gate structure and the second gate structure, wherein the node contact comprises a first end being connected to a top surface of a source/drain region on the first active pattern, and a second end being connected to a top surface of a gate electrode of the second gate structure, the second end of the node contact being shifted relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

“12. The semiconductor device of claim 11, wherein the node contact has a bent line shape, at least a portion of the node contact extending in the second direction in a plan view of the semiconductor device.

“13. The semiconductor device of claim 11, further comprising a third gate structure that is spaced apart from the first gate structure across the node contact and extends across the first active pattern, wherein the second gate structure and the third gate structure are arranged to be spaced apart from each other in the second direction, wherein a pitch between the first and second gate structures is the same as a pitch between the first and third gate structures.

“14. The semiconductor device of claim 13, wherein the first end of the node contact is spaced apart from the first gate structure at a first distance, the second end of the node contact is spaced apart from the first gate structure at a second distance, and the second end of the node contact is spaced apart from the second gate structure at a third distance, and wherein the first distance, the second distance, and the third distance are different from each other.

“15. The semiconductor device of claim 14, wherein the third distance is less than the first distance and the second distance.

“16. The semiconductor device of claim 15, wherein the second distance is greater than the first distance.

“17. The semiconductor device of claim 11, wherein the second end of the node contact includes a portion of the node contact, which is connected to a top surface of a source/drain region on the second active pattern, and a gate contact connected to the top surface of the gate electrode of the second gate structure.

“18. The semiconductor device of claim 17, wherein the gate contact comprises a same material as that of the node contact.

“19. The semiconductor device of claim 17, wherein the gate contact has a top surface at a same height as that of a top surface of the node contact relative to the substrate.

“20. The semiconductor device of claim 11, wherein the second gate structure comprises the gate electrode on the substrate and a gate spacer on a sidewall of the gate electrode, and the gate spacer is between the second end of the node contact and the gate electrode.”

For more information, see this patent application: Kim, Sangyoung; LEE, Hyung Jong; BAE, Deokhan. Semiconductor Devices. Filed April 3, 2019 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190229121%22.PGNR.&OS=DN/20190229121&RS=DN/20190229121

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, South Korea Daily Report, source Geographic Newsletters

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