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MarketScreener Homepage  >  Equities  >  KOREA EXCHANGE  >  SK Hynix Inc    000660   KR7000660001

SK HYNIX INC

(000660)
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Patent Issued for Semiconductor Device And Method Of Manufacturing The Same (USPTO 10,366,922): SK Hynix Inc.

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08/14/2019 | 05:45pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at South Korea Daily Report -- SK Hynix Inc. (Icheon-si, Gyeonggi-do, South Korea) has been issued patent number 10,366,922, according to news reporting originating out of Alexandria, Virginia, by NewsRx editors.

The patent’s inventor is Lee, Nam Jae (Cheongju-si, South Korea).

This patent was filed on January 9, 2017 and was published online on August 12, 2019.

From the background information supplied by the inventors, news correspondents obtained the following quote: “Various embodiments generally relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device including contact plugs and a method of manufacturing the same.

“There technology proposals relating to stacking memory cells over substrates in order to increase the degrees of integration within semiconductor devices. The memory cells stacked over the substrates may be coupled to conductive patterns. The conductive patterns may be arranged over the substrates at different heights. In order to independently apply an electrical signal to the conductive patterns arranged at different heights, contact plugs may be coupled to the conductive patterns. The conductive patterns may be patterned to form a stepped structure to open contact regions of the conductive patterns, and the contact plugs may be coupled to the contact regions of the conductive patterns opened through the stepped structure.

“However, errors may occur when the conductive patterns are patterned into the stepped structure. For example, misalignment may occur between the contact plugs and the conductive patterns due to these errors.”

Supplementing the background information on this patent, NewsRx reporters also obtained the inventor’s summary information for this patent: “In an embodiment, a semiconductor device (e.g. a memory device) may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line and a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line at the first depth. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line at the second depth. The first and the second conductive lines may be first and second word lines, respectively.

“In an embodiment, a semiconductor device (e.g. a memory device) may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line and a second conductive line. A first contact plug of the plurality of contact plugs may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line at the first depth. In addition, the first contact plug may have a second protruding portion protruding from a sidewall of the first pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line at the second depth. The first and the second conductive lines may be first and second select lines, respectively.

“In an embodiment, a semiconductor device (e.g. a memory device) may comprise a plurality of conductive lines and a plurality of contact plugs arranged in a matrix format. The plurality of contact plugs may include a plurality of first contact plugs arranged in a first row of the matrix format, and a plurality of second contact plugs arranged in a second row of the matrix format. Each first contact plug has a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion, so as to be in alignment and contact with a sidewall of a corresponding one of the conductive lines. Each second contact plug has a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion, so as to be in alignment and contact with a sidewall of a corresponding one of the conductive lines. The alignments and contacts between the contact plugs and the conductive lines may be made at different depths of the semiconductor device.”

The claims supplied by the inventors are:

“What is claimed is:

“1. A semiconductor device, comprising: a plurality of conductive lines including a first conductive line and a second conductive line; a plurality of sacrificial insulating layers arranged on sidewalls of the conductive lines; and a plurality of contact plugs including a first contact plug and a second contact plug, the first contact plug having a first pillar portion and a first protruding portion protruding from a part of the first pillar portion overlapped with a sidewall of the first conductive line, in a horizontal direction, so as to be in alignment and contact with the sidewall of the first conductive line, the second contact plug having a second pillar portion and a second protruding portion protruding from a part of the second pillar portion overlapped with a sidewall of the second conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the second conductive line, wherein the plurality of sacrificial insulating layers include an upper sacrificial layer, a lower sacrificial layer and a first sacrificial layer disposed between the upper sacrificial layer and the lower sacrificial layer, wherein the first protruding portion is disposed between the upper sacrificial layer and the lower sacrificial layer to be overlapped with the upper sacrificial layer and the lower sacrificial layer, and wherein the sidewall of the first conductive line, which is not overlapped with the upper sacrificial layer and the lower sacrificial layer, contacts with the first protruding portion.

“2. The semiconductor device of claim 1, wherein the first conductive line and the second conductive line are disposed in different planes, and the first protruding portion and the second protruding portion are disposed in different planes.

“3. The semiconductor device of claim 1, further comprising: insulating layers formed in between the first and the second conductive lines.

“4. The semiconductor device of claim 1, further comprising: insulating layers formed with a gap between adjacent insulating layers and surrounding sidewalls of the first and the second pillar portions.

“5. The semiconductor device of claim 1, wherein the plurality of sacrificial insulating layers include a second sacrificial layer, and wherein the second sacrificial layer is adjacent to and in plane with the second conductive line.

“6. The semiconductor device of claim 5, further comprising: the second sacrificial layer extending to sidewalls of the second protruding portion of the second contact plug.

“7. The semiconductor device of claim 1, further comprising: the first pillar portion of the first contact plug having a first end at a top surface of the first contact plug and a second end at a bottom surface of the first contact plug; and the second pillar portion of the second contact plug having a first end at a top surface of the second contact plug and a second end at a bottom surface of the second contact plug.

“8. The semiconductor device of claim 1, further comprising: the plurality of conductive lines including a third conductive line and a fourth conductive line; and the plurality of contact plugs including a third contact plug, the third contact plug having a third pillar portion, a third protruding portion and a fourth protruding portion, the third protruding portion extending from a part of the third pillar portion overlapped with a sidewall of the third conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the third conductive line, the fourth protruding portion extending from a part of the third pillar portion overlapped with a sidewall of the fourth conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the fourth conductive line.

“9. The semiconductor device of claim 8, wherein the third conductive line and the fourth conductive line are disposed in different planes, and the third protruding portion and the fourth protruding portion are disposed in different planes.

“10. The semiconductor device of claim 8, further comprising: insulating layers formed in between the third and the fourth conductive lines.

“11. The semiconductor device of claim 8, further comprising: insulating layers formed with a gap between adjacent insulating layers and surrounding sidewalls of the third and the fourth protruding portions.

“12. The semiconductor device of claim 8, wherein the plurality of sacrificial insulating layers include a third sacrificial layer and a fourth sacrificial layer, wherein the third sacrificial layer is adjacent to and in plane with the third conductive line, and wherein the fourth sacrificial layer is adjacent to and in plane with the fourth conductive line.

“13. The semiconductor device of claim 12, further comprising: the third sacrificial layer extending to a sidewall of the third protruding portion of the third contact plug; and the fourth sacrificial layer extending to a sidewall of the fourth protruding portion of the third contact plug.

“14. A semiconductor device, comprising: a plurality of conductive lines including a first conductive line and a second conductive line; a plurality of sacrificial insulating layers arranged on sidewalls of the conductive lines, the plurality of sacrificial insulating layers including a first sacrificial insulating layer and a second sacrificial insulating layer; and a plurality of contact plugs including a first contact plug, the first contact plug having a first pillar portion, a first protruding portion and a second protruding portion, the first protruding portion extending from a part of the first pillar portion overlapped with a sidewall of the first conductive line, in a horizontal direction, so as to be in alignment and contact with the sidewall of the first conductive line, the second protruding portion extending from a part of the first pillar portion overlapped with a sidewall of the second conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the second conductive line, wherein the first protruding portion is formed between the first conductive line and the first sacrificial insulating layer, and the second protruding portion is formed between the second conductive line and the second sacrificial insulating layer.

“15. The semiconductor device of claim 14, wherein the first and the second conductive lines comprise first and second select lines, respectively.

“16. The semiconductor device of claim 14, wherein the first conductive line and the second conductive line are disposed in different planes, and the first protruding portion and the second protruding portion are disposed in different planes.

“17. The semiconductor device of claim 14, further comprising: an insulating layer formed in between the first and the second conductive lines.

“18. The semiconductor device of claim 14, further comprising: insulating layers formed with a gap between adjacent sacrificial insulating layers and surrounding a sidewall of the first pillar portion.

“19. A semiconductor device, comprising: a plurality of conductive lines disposed in different planes; a plurality of contact plugs arranged in a matrix format; and a plurality of sacrificial insulating layers arranged on sidewalls of the conductive lines, wherein each of the contact plugs passes through at least one of the sacrificial insulating layers, the contact plugs including: a plurality of first contact plugs arranged in a first row of the matrix format; and a plurality of second contact plugs arranged in a second row of the matrix format, each first contact plug having a first pillar portion and a first protruding portion protruding from a part of the first pillar portion overlapped with a corresponding one of the conductive lines, so as to be in alignment and contact with a sidewall of a corresponding one of the conductive lines, each second contact plug having a second pillar portion and a second protruding portion protruding from a part of the second pillar portion overlapped with a corresponding one of the conductive lines, so as to be in alignment and contact with a sidewall of a corresponding one of the conductive lines, wherein the alignments and contacts between the contact plugs and the conductive lines are made at different depths of the semiconductor device, and wherein the conductive lines are disposed between the first contact plugs and the second contact plugs.

“20. The semiconductor device of claim 19, further comprising: insulating layers formed in between the plurality of conductive lines and surrounding the sidewalls of the first and the second pillar portions.”

For the URL and additional information on this patent, see: Lee, Nam Jae. Semiconductor Device And Method Of Manufacturing The Same. U.S. Patent Number 10,366,922, filed January 9, 2017, and published online on August 12, 2019. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=10,366,922.PN.&OS=PN/10,366,922RS=PN/10,366,922

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, South Korea Daily Report, source Geographic Newsletters

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Financials (KRW)
Sales 2019 25 251 B
EBIT 2019 2 838 B
Net income 2019 2 345 B
Debt 2019 1 639 B
Yield 2019 2,04%
P/E ratio 2019 23,9x
P/E ratio 2020 12,1x
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Capitalization 52 258 B
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Average target price 89 763,89  KRW
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Seok-Hee Lee Chief Executive Officer & Director
Joon-Ho Kim Co-President, Director & Head-Management Support
Tae-Won Chey Chairman-Executive Board
Myung-Young Lee Senior Managing Director & Head-Finance
Sang-Seon Lee Senior MD & Head-Production and Technology
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