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Patent Issued for MTP-Thyristor Memory Cell Circuits And Methods Of Operation (USPTO 10,366,736): Synopsys Inc.

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08/14/2019 | 05:45pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Information Technology Business Daily -- From Alexandria, Virginia, NewsRx journalists report that a patent by the inventors Bill, Colin Stewart (Cupertino, CA); Luan, Harry (Saratoga, CA), filed on September 7, 2017, was published online on August 12, 2019.

The patent’s assignee for patent number 10,366,736 is Synopsys Inc. (Mountain View, California, United States).

News editors obtained the following quote from the background information supplied by the inventors: “This invention is related to integrated circuit devices having memory cell arrays and, in particular, to arrays capable of holding information without power and of being programmed multiple times.

“An MTP (Multiple Times Programmable) device is a type of non-volatile memory device (NVM) that, as the name implies, can be programmed and erased numerous times. Once programmed, an MTP device can hold the programmed information even without power. Memories with MTP devices are found embedded in integrated circuits, such as microcontrollers, in many different types of computer systems, including smart phones, and independently as thumb drives which are carried on one’s person and can be connected externally to a computer system (typically through a USB port).

“It should be noted that often terms, such as MTP device and NVM device, are used interchangeably between the memory array, or the integrated circuit containing the array, and the memory cell, or the transistor-level element which stores programmed information. Hence care should be taken in determining what the term refers to. MTP device as used herein refers to a transistor-level element which stores programmed information unless the context clearly indicates otherwise.

“At the transistor-level, an MTP device is a Field Effect Transistor (FET) device, also often referred to as a MOSFET (metal-oxide-semiconductor FET) in which the threshold voltage V.sub.T is determined by the charges in a charge storage region, such as a floating gate, or a plane or sidewall of charge trapping material in the gate region of transistor device. Nitride-based materials are examples of charge trapping materials and can form charge trapping structures, such as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon layers), formed either as plane or a sidewall.

“MTP memory cells face problems of scaling, i.e., problems resulting from the shrinkage in device feature size, particularly for semiconductor processes having critical dimensions of 40 nm (nanometer) or smaller. These problems include the requirements of thinner oxide layers, lower practical programming and erase voltages, smaller quantities of stored charge, and increasing variations in device parameters and performance, such as leakage and operating currents. Furthermore, Read operations should become faster with smaller features, but better access times are difficult to address in light of these problems of scaling. Furthermore, rather than a conventional NVM device in which the charge is stored in a floating gate, current MTP memory cells envision charge trapping in a sidewall of the device. This results in smaller differences in the threshold voltages between the Programmed and Erased states that must still be discriminated.

“Hence what is needed is a MTP memory cell which can be easily scaled with future processes and which can solve or at least ameliorate the problems above.”

As a supplement to the background information on this patent, NewsRx correspondents also obtained the inventors’ summary information for this patent: “This invention provides an integrated circuit memory cell for an array of memory cells. Each memory cell in the array is capable of holding information by the storage of charge and includes a thyristor having anode and cathode regions and two intermediate regions there between; and an MTP device connected to one of the two intermediate regions of the thyristor and having a charge storage region. The charge in the charge trapping region determines the threshold voltage of the MTP device and controls the switching characteristics of the thyristor. The information held in the memory cell is determined by the switching characteristics of the thyristor.

“The present invention also provides an integrated circuit structure in which a thyristor is formed in a first electrically isolated pocket of the substrate and coupled to a non-volatile memory cell in an adjacent pocket. Additionally, the integrated circuit can include a third pocket, in which a reference non-volatile memory cell having a known state of stored charge is formed. A detector may then be provided for comparing the degree of stored charge of the reference cell with charge stored in the non-volatile data memory cell.

“In another embodiment the integrated circuit includes a plurality of field effect transistors providing logic functions elsewhere on the integrated circuit, the thyristor comprises at least four layers having spacing defined by field effect transistor gates that are not connected to any active potential source.

“In another embodiment, an integrated circuit includes, a semiconductor substrate divided into first and second electrically isolated pockets by a region of insulating material. The first pocket includes a thyristor provided by a buried N-well, a P-well, a shallow N-well, an anode contact to a P-type region within the shallow N-well, and a cathode contact to the buried N-well. The second pocket includes a buried N-well, a P-well, spaced apart source/drain regions in the P-well, a conductive word line overlapping the spaced apart source/drain regions, a charge-trapping device having an electrode that extends between one of the source/drain regions and an additional source/drain region, and electrical contacts to each of the buried N-well, the P-well, each of the source/drain regions and the additional source/drain region. Electrical connections are provided between components in the first pocket and components in the second pocket.

“Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.”

The claims supplied by the inventors are:

“The invention claimed is:

“1. A method of verifying a logic state of a selected data memory cell in an array of interconnected memory cells after programming or erasing the selected data memory cell, comprising: increasing a word line voltage applied to the selected data memory cell and a reference memory cell associated with the selected data memory cell; latching an output of a first sense amplifier at a delayed time after a logic state of an output of a second sense amplifier is switched responsive to increasing the word line voltage, an amount of time between the switching of the logic state of the output of the second sense amplifier and the delayed time representing separation between a threshold voltage of the reference memory cell and a threshold voltage of the selected data memory cell, wherein: when verifying programming of the selected data memory cell, the output of the first sense amplifier is an amplified version of an output of the selected data memory cell, and the output of the second sense amplifier is an amplified version of an output of the reference memory cell, and when verifying erasing of the selected memory cell, the output of the first sense amplifier is an amplified version of the output of the reference memory cell, and the output of the second sense amplifier is an amplified version of the output of the selected data memory cell; and determining whether the selected data memory cell has been programmed, or has been erased based on a value of the latched output of the first sense amplifier.

“2. The method of claim 1, wherein the logic state of the second sense amplifier is switched when an input voltage to the second sense amplifier rises above a predetermined amount.

“3. The method of claim 2, wherein the predetermined amount comprises 200 mV.

“4. The method of claim 1, further comprising: re-programming the selected data memory cell if the selected data memory cell has not been verified to be programmed; or re-erasing the selected data memory cell if the selected data memory cell has not been verified to be erased.

“5. The method of claim 1, wherein the word line voltage is ramped at a rate less than 100 mV/s.

“6. The method of claim 1, wherein a voltage on a common electrode for gates of transistors in the selected data memory cell and a reference memory cell associated with the selected data memory cell is increased responsive to increasing the word line voltage.

“7. The method of claim 1, wherein the amount of time is predetermined.

“8. A memory cell reading circuitry for reading a selected memory cell selected from an array of interconnected memory cells, comprising: a ramp generation block configured to increase a word line voltage applied to the selected memory cell and a reference memory cell corresponding to the selected memory cell, the word line voltage starting at an initial voltage; a first differential sense amplifier configured to receive an output of the selected memory cell, and generate an amplified version of the output of the selected memory cell; a circuit configured to generate a signal responsive to an output of the reference memory cell reaching a first predetermined voltage level, the circuit comprising a pulse generation circuit configured to generate a pulse signal responsive to an output of the reference memory cell reaching the first predetermined voltage level, the word line voltage returning to the initial voltage at an end of the pulse signal; and a latch circuit configured to latch the amplified version of the output of the selected memory cell responsive to receiving the signal generated by the circuit, the latched amplified version of the output of the selected memory cell representing a logic state of the selected data memory cell.

“9. The memory cell reading circuitry of claim 8, wherein the first differential sense amplifier comprises a first input configured to receive the output of the selected data memory cell, and a second input configured to receive a first reference voltage.

“10. The memory cell reading circuitry of claim 9, wherein the first differential sense amplifier is configured to receive the output of the selected data memory cell through a bit line connected to the selected data memory cell.

“11. The memory cell reading circuitry of claim 10, wherein the bit line is connected to a cathode of a thyristor of the selected data memory cell.

“12. The memory cell reading circuitry of claim 8, wherein the circuit comprises a second differential sense amplifier having an output connected to the pulse generation circuit, a first input configured to receive the output of the reference memory cell and a second input configured to receive a second reference voltage, the second reference voltage equal to the first predetermined voltage level.

“13. The memory cell reading circuitry of claim 12, wherein the first input of the second differential sense amplifier is configured to receive the output of the reference memory cell through a bit line connected to the reference memory cell.

“14. The memory cell reading circuitry of claim 13, wherein the bit line is connected to a cathode of a thyristor of the reference memory cell.

“15. The memory cell reading circuitry of claim 8, wherein the circuit comprises a second differential sense amplifier having an output connected to the pulse generation circuit, a first input configured to receive the output of the reference memory cell and a second input configured to receive a second reference voltage, the first and second reference voltages equal to the first predetermined voltage level.

“16. The memory cell reading circuitry of claim 8, wherein the initial voltage comprises zero voltage.

“17. The memory cell reading circuitry of claim 8, the first differential sense amplifier is configured to compare the output of the selected data memory cell against a second predetermined voltage level.

“18. The memory cell reading circuitry of claim 17, wherein the first predetermined voltage level is equal to the second predetermined voltage level and the logic state latched is dependent upon whether the output of the selected data memory cell reaches the first predetermined voltage level earlier than the output of the reference memory cell reaches the first predetermined voltage level.

“19. The memory cell reading circuitry of claim 18, wherein the logic state latched is in a programmed state when the output of the reference memory cell reaches the first predetermined voltage level earlier than the output of the selected data memory cell reaches the first predetermined voltage level.

“20. The memory cell reading circuitry of claim 18, wherein the logic state latched is in an erased state when the output of the selected data memory cell reaches the first predetermined voltage level earlier than the output of the reference memory cell reaches the first predetermined voltage level.”

For additional information on this patent, see: Bill, Colin Stewart; Luan, Harry. MTP-Thyristor Memory Cell Circuits And Methods Of Operation. U.S. Patent Number 10,366,736, filed September 7, 2017, and published online on August 12, 2019. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=10,366,736.PN.&OS=PN/10,366,736RS=PN/10,366,736

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Information Technology Business Daily, source Technology Newsletters

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