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MarketScreener Homepage  >  Equities  >  TAIWAN STOCK EXCHANGE  >  Winbond Electronics Corp.    2344   TW0002344009

WINBOND ELECTRONICS CORP.

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Japan - Researchers Submit Patent Application, “Semiconductor Storage Device, Operating Method Thereof And Analysis System”, for Approval (USPTO 20190227123): Winbond Electronics Corp.

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08/14/2019 | 05:39pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Daily Asia Business -- From Washington, D.C., NewsRx journalists report that a patent application by the inventors Senoo, Makoto (Kanagawa, Japan); Suito, Katsutoshi (Kanagawa, Japan), filed on October 8, 2018, was made available online on July 25, 2019.

The patent’s assignee is Winbond Electronics Corp. (Taichung City, Taiwan).

News editors obtained the following quote from the background information supplied by the inventors: “Technical Field

“The disclosure relates to a semiconductor storage device such as a flash memory. More particularly, the disclosure relates to an analysis of a defect of a semiconductor storage device.

“Description of Related Art

“In a semiconductor device, a defect may exist in routing or circuits and the like owning to a defective manufacturing process. Through analyzing such defect and identifying the abnormal batches before the products are shipped, productivity can thereby be increased. For instance, in a defective product analysis method of a semiconductor memory according to Japanese Patent Publication No. 2010-135030, a defect address of a storage array may be determined through a test circuit, a defect mode may be determined through analyzing the defect address, and the deteimined defect mode is output to the outside.

“In certain types of analysis devices such as an emission microscope (EMMI) or an optical beam induced resistance change (OBIRCH), a camera is included to capture the entire semiconductor chip. The position of the abnormal leakage current on the semiconductor chip can be detected through analyzing the captured image data, and the position where the abnormal current is detected on the image data can be enabled to emit light.

“An analysis device of one of these types includes a terminal configured for a Vcc power supply, an external terminal configured for chip selection, and a terminal configured for GND. The terminals can individually be electrically connected to corresponding external terminals of the semiconductor chip, and in this way, the semiconductor chip is in the standby state, and the leakage current can be detected at this time.

“Nevertheless, recently, the leakage current generated by a specific operation of a semiconductor memory is also required to be detected. For instance, a short circuit caused among the bit lines when pre-charging is performed to the global bit lines by the flash memory in a reading operation, a short circuit caused among the word lines when a programming pulse is applied in a programming operation, and the leakage caused when an erasing voltage is applied to a well in an erasing operation etc. are required to be detected.

“Nevertheless, in an existing analysis device, a terminal configured to output a command to the semiconductor chip is not included (i.e., an interface configured to control the semiconductor chip is not included), the abnormal leakage current caused by a specific operation performed by the semiconductor memory thus cannot be detected.”

As a supplement to the background information on this patent application, NewsRx correspondents also obtained the inventors’ summary information for this patent application: “The disclosure provides a semiconductor storage device, an operating method of the semiconductor storage device, and a defect analysis system capable of analyzing a defect caused by a specific operation to solve the foregoing problem.

“An operating method provided by an embodiment of the disclosure is an operating method of a semiconductor storage device including a controller configured to control an operation related to a storage array. The controller determines that whether the semiconductor storage device is in a specific mode based on a signal supplied to an external terminal. The controller executes a break sequence to stop the operation in a process of executing the operation related to the storage array when determining that the semiconductor storage device is in a specific mode.

“A semiconductor storage device provided by an embodiment of the disclosure includes a storage may, a controller configured to control an operation related to the storage array, and an external terminal. The controller includes a determination part and an execution part. The determination part determines that whether the semiconductor storage device is in a specific mode based on the signal supplied to the external terminal. The execution part executes a break sequence to stop the operation in a process of executing the operation related to the storage array when the determination part determines that the semiconductor storage device is in a specific mode.

“An analysis system provided by an embodiment of the disclosure includes the semiconductor storage device and an analysis device connected to the semiconductor storage device. The analysis device supplies a power voltage to the semiconductor storage device and analyzes a portion in the semiconductor storage device where an abnormal current flows. In an embodiment of the disclosure, the analysis device includes a part to visualize the portion where the abnormal current flows.

“To sum up, since the break sequence is executed in a specific mode, the analysis of the expected operation performed by the semiconductor storage device may be easily performed. In particular, when the interface configured to control the memory is absent between the analysis device and the semiconductor storage device (the semiconductor chip), the determination of whether the semiconductor storage device is in a specific mode can be made based on the signal supplied to the external terminal.

“To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.”

The claims supplied by the inventors are:

“1. An operating method of a semiconductor storage device, the semiconductor storage device comprising a controller configured to control an operation related to a storage array, wherein the controller determines that whether the semiconductor storage device is in a specific mode based on a signal supplied to an external terminal, and the controller executes a break sequence to stop the operation in a process of executing the operation related to the storage array when determining that the semiconductor storage device is in a specific mode.

“2. The operating method as claimed in claim 1, wherein the break sequence comprises the following steps: selecting the operation related to the storage array; executing the selected operation; and stopping the operation at a selected timing.

“3. The operating method as claimed in claim 2, wherein the break sequence comprises the following steps: reading selection information configured to select the operation related to the storage array and stop information configured to stop the operation at the selected timing from a predetermined storage region.

“4. The operating method as claimed in claim 1, wherein the controller executes the break sequence when the semiconductor storage device is determined to be in a power-on mode based on a power voltage supplied to the external terminal.

“5. The operating method as claimed in claim 2, wherein the controller executes the break sequence when the semiconductor storage device is determined to be in a power-on mode based on a power voltage supplied to the external terminal.

“6. The operating method as claimed in claim 1, wherein the operating method further comprises the following steps: setting whether to execute the break sequence, executing the break sequence by the controller when execution of the break sequence is set.

“7. The operating method as claimed in claim 2, wherein the operating method further comprises the following steps: setting whether to execute the break sequence, executing the break sequence by the controller when execution of the break sequence is set.

“8. The operating method as claimed in claim 3, wherein the controller stops reading a code from a read only memory and stops the operation based on an address contained in the stop information.

“9. The operating method as claimed in claim 1, wherein the controller stops the operation when bit lines are pre-charging in a reading operation of the storage array.

“10. The operating method as claimed in claim 2, wherein the controller stops the operation when bit lines are pre-charging in a reading operation of the storage array.

“11. A semiconductor storage device, comprising: a storage array; a controller, configured to control an operation related to the storage array; and an external terminal, the controller comprising a determination part, determining that whether the semiconductor storage device is in a specific mode based on a signal supplied to the external terminal; and an execution part, executing a break sequence to stop the operation in a process of executing the operation related to the storage array when the determination part determines that the semiconductor storage device is in a specific mode.

“12. The semiconductor storage device as claimed in claim 11, wherein the determination part determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to the external terminal, and the execution part executes the break sequence when the semiconductor storage device is determined to be in the power-on mode.

“13. The semiconductor storage device as claimed in claim 11, wherein the execution part reads selection information configured to select the operation related to the storage array and stop information configured to stop the operation at a selected timing from a predetermined storage region, and the execution part executes the operation according to the selection information and stops the operation according to the stop information.

“14. The semiconductor storage device as claimed in claim 12, wherein the execution part reads selection information configured to select the operation related to the storage array and stop information configured to stop the operation at a selected timing from a predetermined storage region, and the execution part executes the operation according to the selection information and stops the operation according to the stop information.

“15. The semiconductor storage device as claimed in claim 11, wherein the semiconductor storage device further comprises a setting part configured to set whether to execute the break sequence, and the execution part executes the break sequence when the setting part sets execution of the break sequence.

“16. The semiconductor storage device as claimed in claim 13, wherein: the execution part stops reading a code from a read only memory and stops the operation based on an address contained in the stop information.

“17. An analysis system as claimed in claim 11, comprising the semiconductor storage device and an analysis device connected to the semiconductor storage device, wherein the analysis device supplies a power voltage to the semiconductor storage device and analyzes a portion in the semiconductor storage device where an abnormal current flows.

“18. The analysis system as claimed in claim 17, wherein the analysis device comprises a part to visualize the portion where the abnormal current flows.”

For additional information on this patent application, see: Senoo, Makoto; Suito, Katsutoshi. Semiconductor Storage Device, Operating Method Thereof And Analysis System. Filed October 8, 2018 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190227123%22.PGNR.&OS=DN/20190227123&RS=DN/20190227123

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Daily Asia Business, source Geographic Newsletters

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