Cadence Design Systems, Inc. and Samsung Foundry announced development of a full portfolio of Memory and Interface IP, and expanded certification of Cadence?s agentic AI digital, custom, 3D-IC and system design and analysis (SDA) flows for Samsung Electronics Co., Ltd.'s second-generation 2nm process technology. This collaboration delivers a signoff-ready platform for next-generation AI infrastructure and physical AI designs across data center, edge and intelligent devices. Building on the companies?

2025 announcement of certified Cadence tools and IP on multiple Samsung Electronics Co., Ltd. nodes, including second-generation 2nm, this new multi-year agreement further broadens the Cadence portfolio of Memory and Interface IP, including NVIDIA NVLink-C2C-enabled interconnect and CUDA-X GPU-accelerated libraries spanning high-speed SerDes, PCIe, UCIe and all leading memory interfaces on second-generation 2nm. It also deepens enablement of certified Cadence flows so ecosystem partners can implement large AI, HPC and advanced system designs with higher performance, lower power and faster time to tapeout. Cadence Design Systems, Inc. and Samsung Electronics Co., Ltd. deliver a comprehensive certified flow on second-generation 2nm, including Cadence?s Innovus Implementation System for digital implementation, Virtuoso Studio for analog and custom design, Integrity 3D-IC Platform for full 3D-IC system planning and implementation, Voltus IC Power Integrity Solution for power integrity and system-level power analysis, and Quantus Extraction Solution and Tempus Timing Solution for signoff.

Cadence Design Systems, Inc. enables key second-generation 2nm design features, including the Innovus system and Genus Synthesis Solution?s glitch power optimization in the place and route flow, and a smart hierarchical flow to achieve optimal performance, power, and area (PPA) and turnaround time (TAT). Samsung Electronics Co., Ltd. 3D Cube-H design is enabled with a full system planning, implementation and signoff flow for hybrid copper bonding (HCB) technology, including Cadence Cerebrus Intelligent Chip Explorer, Integrity 3D-IC, Innovus Implementation, Voltus IC Power Integrity (ERA) and Pegasus Verification System. It includes silicon interposer auto-routing and optimization, and ensures tighter connectivity between analysis, signoff, and verification, with the Tempus and Pegasus solutions providing trusted, confident signoff.

Cadence Design Systems, Inc. and Samsung Electronics Co., Ltd. will highlight their enhanced partnership and design enablement during the Samsung Advanced Foundry Ecosystem (SAFE) 2026 event, featuring technical sessions and demonstrations showcasing second-generation 2nm and 3D-IC design flows for GPU-accelerated AI workloads.