Cadence announced a Chiplet Spec-to-Packaged Parts ecosystem to reduce engineering complexity and accelerate time to market for customers developing chiplets targeting physical AI, data center, and high-performance computing (HPC) applications. Initial IP partners joining Cadence include Arm, Arteris, eMemory, M31 Technology, Silicon Creations and Trilinear Technologies, as well as silicon analytics partner proteanTecs. To help reduce risk and streamline customer adoption, Cadence is collaborating with Samsung Foundry to build out a silicon prototype demonstration of the Cadence®?
Physical AI chiplet platform, including pre-integrated partner IP on the Samsung Foundry SF5A process. Cadence's Chiplet Spec-to- Packaged Parts ecosystem reduces engineering complexity and accelerates time to market for customers developing Chiplets targeting physical AI, Data center, and HPC applications. Extending their longstanding history of close collaboration, Cadence and Arm are working together to accelerate innovation across physical and infrastructure AI applications.
Cadence will leverage the advanced Arm®? Zena?? Compute Subsystem (CSS) and other essential IP to enhance Cadence's Physical AI chiplet platform and Chiplet Framework.
The resulting new Cadence solutions accommodate the demanding next-generation edge AI processing requirements for automobiles, robotics and drones, as well as the needs of standards-based I/O and memory chiplets for data center, cloud and HPC applications. The alliances reduce engineering complexities, offer customers a low-risk path to advanced chiplet adoption and pave the way for smarter, safer and more efficient systems. An earlier prototype of the Cadence base system chiplet, which is part of the Cadence Physical AI chiplet platform and incorporates the Cadence chiplet framework, UCIe 32G, and LPDDR5X IP, has already been fully silicon validated.
