Marvell Technology, Inc. announced that it will demonstrate PCIe®? 8.0 SerDes running at 256 gigatransfers-per-second (GT/s) data rate in the Marvell booth #904 at DesignCon 2026, February 24 to 26 at the Santa Clara Convention Center in Santa Clara, California. As AI workloads continue to drive a massive expansion in data center infrastructure requirements, PCIe technology continues to evolve to deliver higher bandwidth for in-chassis, in-rack and across-rack connectivity.

Expected to be finalized by 2028, the PCIe 8.0 specification is expected to double the bandwidth of the PCIe 7.0 specification for up to 1 TB/s of bidirectional bandwidth, supporting demanding applications including AI, machine learning, high-speed networking and other data-intensive workloads. In preparation for the PCIe 8.0 specification, hyperscalers and cloud data center operators can start pathfinding now, solidifying strategies to re-architect their infrastructure and take full advantage of the new specification when it is released. Providing an early demonstration of the PCIe 8.0 specification with the TE Connectivity AdrenaLINE Catapult connector at DesignCon 2026, Marvell is committed to helping the industry scale beyond traditional copper interconnects.

Enabling low power, low latency and low bit-error-rate transmission over copper and optical channels, the Marvell®? Alaska®? P PCIe 6.0 retimer and its PCIe 7.0 and PCIe 8.0 SerDes technology will deliver the scalability, power efficiency and high performance required for next-generation infrastructure to support tomorrow's AI and data center bandwidth demand.