Advanced Semiconductor Engineering Inc. announced the industry's first Fan-Out Chip on Substrate Chip First (FOCoS-CF) with encapsulant-separated redistribution layer (RDL) and Chip Last (FOCoS-CL) semiconductor packaging solution that elevates the performance for High Performance Computing (HPC), under the ASE VIPack platform. This progression of fan-out technology offers breakthrough board level reliability and exceptional electrical performance while meeting integration requirements for networking and artificial intelligence applications that demand greater memory and compute power. The growing demand for high density, high speed, and low latency of chip-to-chip interconnect is driving a new level of packaging innovations such as FOCoS-CF and FOCoS-CL.
This combined FOCoS-CF and FOCoS-CL portfolio addresses the limitations of traditional flip-chip packages where a single SoC is assembled on a substrate by enabling multi-chip and chiplet integration where two or more chips can be reconstituted into a fan-out module and then assembled on a substrate. Encapsulant-separated RDL is a chip first technology that helps to address some of the die placement and design rule related issues seen with the traditional reconstituted wafer process technology. FOCoS-CF using encapsulant-separated RDL enables improved Chip Package Interaction (CPI), lessened mechanical stress risk over the chip edge at RDL, and better high frequency signal integrity.
There are also advanced design rule improvements that enable a higher IO density by up to 10x existing by reducing pad pitches, while creating heterogeneous integration opportunities across chips from varying nodes and different fabs. Data shows that FOCoS-CL is particularly effective for High Bandwidth Memory (HBM) integration, a technology area of growing significance given its ability to optimize power efficiency and space savings. As demand for HBM continues to grow within the HPC, server, and networking markets, FOCoS-CL innovation delivers crucial performance and footprint advantages.
Heterogeneous integration through advanced packaging technology enables chiplet integration with separate designs and different manufacturing process nodes within a single package. It provides advancement for greater system intelligence, better connectivity, and higher performance at a more manageable cost while delivering a compelling value proposition for yield improvement and IP reuse. ASE's FOCoS portfolio including FOCoS-CF using encapsulant-separated RDL and FOCoS-CL, aligns with market demand as both solutions provide different chips and flip-chip devices to be packaged on a high pin count BGA substrate, allowing the system and package architects to design the optimal package integration solution for their product strategy, value proposition, and time-to-market.
FOCoS packaging technology enables chiplet integration with multiple RDL interconnects up to five layers, a smaller RDL L/S of 1.5/1.5µm, and a large fan-out module size of 34x50mm2. It also provides a wide portfolio integration, such as an application-specific integrated circuit (ASIC) with high-bandwidth memory (HBM) and ASIC with Serdes across many segments of HPC, networking, artificial intelligence/machine learning (AI/ML) and the cloud. Furthermore, FOCoS has demonstrated better electrical performance and lower cost than 2.5D Si TSV because of the elimination of the Si interposer along with reducing parasitic capacitance.