Cadence Design Systems, Inc. announced that Cadence® IP for GDDR6 is silicon proven on TSMC's N5 process technology, exceeding Cadence's previous 16Gbps designs. Targeted for very high-bandwidth memory applications, including hyperscale computing, 5G communications, automotive and consumer, the GDDR6 IP consists of Cadence PHY and controller design IP and Verification IP (VIP). GDDR6 is particularly well suited for the memory interface in artificial intelligence/machine learning (AI/ML) chips, which are proliferating due to the growing number of AI inferencing applications.
Customers can speed development and reduce risk when using Cadence and TSMC technologies to design these chips that connect to GDDR6 memory. The Cadence IP for GDDR6 at TSMC N5 operating at 22Gbps offers more than 2X the data rate of other latest generation standards like DDR5 and LPDDR5 and is 37% faster than Cadence's previous 16Gbps designs. An improved architecture allows up to 22Gbit/sec bandwidth per pin704Gbit/sec per chipacross the full range of operating conditions, with low operational power and idle power as well as a low bit-error rate (BER) for higher reliability and greater bandwidth.
The corresponding GDDR6 controller IP offers a variety of performance and reliability features derived from Cadence's DDR controller designs.