Cadence Design Systems, Inc. announced that Microchip has deployed the Cadence® Palladium® Z2 Enterprise Emulation Platform for the development of their next generation ASIC products targeting high performance and scalable SoC solutions for data centers. The Palladium Z2 platform provided Microchip with 2X better emulation capacity, enabling more simultaneous users and 1.5X greater performance gains versus the previous generation emulator while maintaining full compatibility with existing emulation setups and use models. The Palladium Z2 platform provides an early model of the ASIC for Microchip's software and firmware development teams, which is essential to meeting their goal of successful first-pass silicon and software integration.

Leveraging the congruency of the Palladium and Cadence Protium™ Enterprise Prototyping databases, Microchip saved several weeks of FPGA prototyping bring-up and hardware and software integration debugging time. In addition to providing the same RTL databases, the Palladium and Protium dynamic duo offers design environments that share the same in-circuit and virtual interfaces, making the debug process completely seamless and transparent to software and hardware engineers. The Palladium Z2 Enterprise Emulation Platform and Protium X2 Enterprise Prototyping system are part of the Cadence verification full flow and support the company's Intelligent System Design™ strategy.

The Cadence verification full flow is comprised of core engines and verification fabric technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments. For more information on the Palladium Z2 platform, please visit www.cadence.com/go/palladiumz2cs.