Cadence announced the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on the TSMC N3 process. The new solution addresses the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud. The Cadence DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence's proven and highly successful DDR5 and GDDR6 product lines.
With multiple engagements underway with leading AI, HPC and data center customers, this IP solution is already demonstrating its early leadership. The Cadence DDR 5 MRDIMM IP design is validated in hardware using the most recently available MRDIMMs (Gen2), achieving a best-in-class 12.8Gbps data rate that doubles the bandwidth using current DDR5 6,400Mbps DRAM parts. The DDR5 IP memory subsystem is based on Cadence's silicon-proven, high-performance architecture, ultra-low latency encryption and RAS features.
The DDR5 MRDIMM Gen2 IP is designed to enable advanced SoCs and chiplets with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements. Cadence's DDR5 controller and PHY have been verified with Cadence's Verification IP (VIP) for DDR to provide rapid IP and SoC verification closure. Cadence VIP for DDR5 includes a complete solution from IP to system-level verification with DFI VIP, DDR5 memory model and System Performance Analyzer.
For more information on the new solution, visit the Cadence DDR5 MRDimM PHY and controller page.
