Cadence Design Systems, Inc. announced the new Cadence Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, a revolutionary digital twin platform that builds on the success of the Palladium Z2 and Protium X2 systems to tackle escalating system and semiconductor design complexity, and to accelerate the development timeline for the most advanced SoCs. Palladium and Protium systems have long been trusted by market-shaping AI, automotive, hyperscale, networking and mobile chip companies to deliver the highest throughput pre-silicon hardware debug and pre-silicon software validation. Targeted at the multi-billion-gate designs, the new Palladium Z3 and Protium X3 systems set a new standard of excellence, providing customers with more than a 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems, enabling faster design bring-up and shortening overall time to market.

The Palladium Z3 and Protia X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance. The systems are powered by the NVIDIA BlueField DPU and NVIDIA Quantum InfiniBand networking platforms and maintain congruency when transitioning between the two systems and transitioning from virtual to physical interfaces and vice versa. With the Palladium Z3 system's new domain-specific apps, users have access to the most complete offering for managing increasing system and semiconductor design complex, improving system-level accuracy, and accelerating low-power verification.

The domain-specific apps include the industry's first 4-State Emulation App, the Real Number Modeling App, and the Dynamic Power Analysis App.