DuPont

Semiconductor

Technologies

A Global Innovation Leader

Investor Presentation

September 22, 2021

Semiconductor Technologies: At a glance

INDUSTRY-LEADING PORTFOLIO TARGETING ATTRACTIVE END-MARKETS

BY PRODUCT LINE*

CMP Technologies

BY GEOGRAPHY*

~2,000

$1.8B*

Lithography

COLLEAGUES

Advanced Cleans

Advanced Packaging

Sales Mix: 90% Consumables, 10% Permanent Materials

BY MARKET SEGMENT*

5G/Communication

High Perf Computing

$1.8B* Consumer Electronics

Industrial

Automotive

15%8%

77%

7

MANUFACTURING SITES

~9%

R&D/REVENUE

* Reflects 2020 net sales of the Semiconductor Technologies business.

2

Semiconductor Technologies: At a glance

STRONG FINANCIAL PROFILE AND GROWTH STRATEGY

NET SALES

GROWTH STRATEGY

2019

2020

2021E**

  • Resilient sales based on wafer starts and spec'd in products
  • Consistently outperform market by 200-300 basis points
  • Growth accelerating in 2020 and 2021

Partner with customers to

Expand addressable

optimize product and

market through technology

process performance

transitions

Continue to invest in

Build R&D, application

leading-edge technology

engineering and

manufacturing capabilities

close to customer

Pursue attractive bolt-on acquisitions in high-value adjacencies

* Compound Annual Growth Rate.

3

** 2021E reflects the Company's estimate based on assumptions included as part of the Company's guidance provided as part of its second quarter 2021 earnings call held on August 3, 2021.

Megatrends driving strong surge in semiconductor demand and investment

MEGATRENDS

High-

AI/Big Data/

Performance

Machine

Computing

Learning

5G Connectivity/

Autonomous

IoT

Vehicles

GROWING SEMICONDUCTOR DEMAND

Silicon Shipments (MSI)

Consistent market

growth of 4-6%

2010

2015

2020

2025

Capital Spending

Fab investment

supporting

transitions to

leading edge

2010

2015

2020

2025

Source: SEMI, IC Insights and internal company estimates

4

Technology roadmap creating high-value material challenges

DuPont's portfolio uniquely positioned to enable both smaller nodes AND more complex packaging

Chip package complexity

Smaller, taller, and more complex structures require:

Atomic level planarization

Impurities as low as <1 PPT*

Feature sizes at 5nm and

Ultra low defectivity

below

…all at scale with high reliability

Leading-edge technologies require -

  • Better Performance
  • Lower Power
  • Smaller Area

Chip and wafer architecture, process complexity and material intensity will drive more materials content

*PPT: Parts per Trillion

5

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Disclaimer

DuPont de Nemours Inc. published this content on 22 September 2021 and is solely responsible for the information contained therein. Distributed by Public, unedited and unaltered, on 22 September 2021 16:11:04 UTC.