Keysight Technologies, Inc. announced the launch of Chiplet PHY Designer 2025, its latest solution for high-speed digital chiplet design tailored to AI and data center applications. The enhanced software introduces simulation capabilities for the Universal Chiplet Interconnect Express (UCIe) 2.0 standard and adds support for the Open Computer Project Bunch of Wires (BoW) standard. As an advanced, system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, streamlining the path to tapeout.
Key Benefits of the Chiplet PHY Designer 2025: Ensures Interoperability: Verifies designs meet UCIe 2.0 and BoW standards, enabling seamless integration across advanced packaging ecosystems. Accelerates Time-to-Market: Automates simulation and compliance testing setup, such as Voltage Transfer Function (VTF), simplifying chiplet design workflows. Improves Design Accuracy: Provides insight into signal integrity, bit error rate (BER), and crosstalk analysis, reducing risks of costly silicon re-spins. Optimizes Clocking Designs: Supports advanced clocking scheme analysis, such as quarter-rate data rate (QDR), for precise synchronization in high-speed interconnects.