Synopsys, Inc. announced that Fusion Compiler has been deployed by Arm to enable optimal power, performance and area (PPA) on next-generation Arm® Neoverse™ V1 and N2 infrastructure cores. The latest advances in the Fusion Compiler solution extend the unique benefits of its single-shell, hyper-convergent optimization architecture, enabling designers to extract the maximum performance per watt on their Arm Neoverse-based system-on-chip (SoC) designs targeting broad-market applications including data center infrastructure, high-performance computing, 5G and AI. The Synopsys and Arm reference methodology is immediately available through QuickStart Implementation Kits for these new cores providing an accelerated path to design closure and bring-up. Synopsys' Fusion Compiler RTL-to-GDSII solution is uniquely architected to enable design teams to achieve the optimal levels of PPA in the most convergent manner to ensure the fastest and most predictable time-to-results. It utilizes a highly scalable, unified data model and comprises an analysis backbone that leverages technology from the industry's golden-signoff analysis tools, all within a single, integrated shell, enabling unique customized flows for best quality of results (QoR) and signoff correlation. The Fusion Compiler solution's interleaved optimization engines ensure that critical PPA metrics are optimized efficiently and effectively throughout the full implementation flow. Additionally, its unique architecture is augmented by "machine learning everywhere" technologies, enabling new levels of productivity and QoR.