Synopsys, Inc. announced that Chelsio has adopted its silicon-proven DesignWare® 56G Ethernet PHY IP to accelerate development of Chelsio's System-on-Chip (SoC) design targeting high-performance smart network interface card (NIC) and server applications. Chelsio selected the Synopsys DesignWare 56G Ethernet PHY IP due to its support for a wide range of data rates from 1.25 Gbps to 56 Gbps across standards such as Ethernet, PCI Express, OIF, and JESD. The DesignWare 56G Ethernet PHY with firmware-controlled algorithms including continuous calibration and adaptation (CCA) delivers robust performance across a range of voltage and temperature variations. The Ethernet verification IP and source code test suites enable the design and verification of SoCs with ease-of-use and optimum performance, resulting in accelerated verification closure. To speed development of high-performance computing SoCs, Synopsys provides companies like Chelsio with the industry's most comprehensive IP solutions, including 56G and 112G Ethernet PHYs, DDR5, PCI Express 5.0, die-to-die USR/XSR and HBI PHYs, Compute Express Link (CXL), and CCIX.