Spirent Communications plc announced a collaboration with Synopsys to deliver a networking system-on-chip (SoC) verification solution to bridge the gap between pre- and post-silicon verification. The Spirent Chip Design Verification Solution speeds up the entire silicon development lifecycle and delivers significant cost savings by identifying and addressing issues in the IC design phase and before manufacturing starts. Combining network testing technology from the leading Ethernet test company with an emulation system provides more accurate and faster verification for Ethernet SoCs.

Spirent's TestCenter platform is a networking traffic generator, providing automated, scalable and accurate Ethernet test patterns, which are a necessity for networking ASIC and SoC verification engineers. It is tightly integrated with Synopsys ZeBu® Server, a leading emulation system, enabling pre-silicon SoC validation from 1G to 800G. The integration between the traffic generator and ZeBu Server is time-synced, which allows accurate and realistic Layer 2-3 traffic generation and real-time results analysis.

Leveraging the Spirent Chip Design Verification Solution in all phases of the chipset ecosystem provides: Improved operational efficiency and flexibility using virtualized testbeds. Reduced complexity of network testing through actionable analytics and intuitive reporting. Automation and reusability of test configurations between pre- and post-silicon teams.