Synopsys, Inc. announced its collaboration with Intel to achieve successful system-level interoperability between the SynopsysDesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids). The full-system interoperability, a key milestone in Synopsys and Intel's ongoing collaboration, enables the ecosystem to confidently use the companies' proven technologies to accelerate development of their PCIe 5.0-based products in high-performance computing and AI applications. The DesignWare IP for PCI Express 5.0 has been licensed over a hundred times by customers across all key market segments, delivering the lowest latency and high throughput IP compared to other solutions in the industry. Availability and Additional Resources: The DesignWare Controller, PHY, and Verification IP for PCIe 5.0 in a wide range of FinFET processes from 16-nm to 5-nm is available now.