Synopsys, Inc. announced that Graphcore achieved first-pass silicon success using the IC Compiler™ II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an 7nm advanced process technology. Graphcore leveraged Synopsys IC Compiler II ultra-high capacity architecture and innovative technologies for AI-hardware design resulting in an accelerated implementation of their massive AI processor. Synopsys' RTL-to-GDS flow with power optimization capabilities along with embedded golden signoff technologies like PrimeTime® delay calculator, provided Graphcore design teams superior out-of-the-box PPA metrics, and the fast design closure. The second-generation Colossus GC200 IPU from Graphcore is a sophisticated chip, integrating 1,472 independent processor cores and more than 900 megabytes of on-chip memory to deliver superior parallel processing power for data-center scale AI applications. Synopsys' IC Compiler II, with its AI-design focused capabilities, includes top-level interconnect planning, logic restructuring, congestion-driven mux optimization and full-flow concurrent clock and data optimization delivers best-in-class PPA for the highly repetitive, MAC-based topologies typical in complex AI accelerator chips. Further, its native, high-capacity data model with adaptive abstraction and distributed implementation can efficiently handle multi-billion instance designs with quick turn-around-time. With a unique, golden signoff engine backbone, IC Compiler II delivers highest correlation and hyper-convergent design, to further accelerate design turnaround time.