Synopsys, Inc. announced its new DesignWare® Die-to-Die Controller IP, which complements the company's existing 112G USR/XSR PHY IP for a complete die-to-die IP solution. With the complete IP solution, designers benefit from a low-latency, high-bandwidth die-to-die connectivity offering that addresses the increased workload and faster data movement demands of high-performance computing, artificial intelligence (AI) and networking SoCs. The DesignWare Die-to-Die Controller and PHY IP are part of the company’s multi-die solution, consisting of HBM IP and 3DIC Compiler, accelerating SoC designs requiring advanced packaging. The DesignWare Die-to-Die Controller provides error recovery mechanisms such as optional forward-error correction and cyclic redundancy check for higher data integrity and link reliability. The DesignWare Die-to-Die controller's flexible configuration supporting the AMBA® CXS and AXI protocols allows coherent and non-coherent data communication for easy integration into Arm-based and other high-performance SoCs. The DesignWare Die-to-Die Controller with support for up to 1.8Tb/s PHY bandwidth addresses high-performance computing demands of SoCs requiring robust die-to-die connectivity. The company’s broad DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. The company’s extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time-to-market. The DesignWare Die-to-Die Controller IP is available now to early adopters. The company’s DesignWare Die-to-Die USR/XSR PHY IP in 12nm, 7nm and 5nm processes are available now with a roadmap to 3nm. The HBI PHY IP in 7nm and 5nm processes are available now.