Synopsys, Inc. announced the latest stages in its ongoing collaboration with IBM Research's AI Hardware Center to advance the development of chip architectures and design methodologies critical to the next generation of AI chips. Synopsys is working closely with IBM to implement the latest AI Hardware Center technologies in full chip solutions, which could be commercialized in the near future. Their unique collaboration was established last year, leveraging the rich expertise of IBM's renowned research organization, and combining the efforts of multiple commercial partners, as well as academic and government entities that support the initiative. The overarching goal of the work with IBM is to achieve a continued trend of annual doubling of the AI compute performance for a decade or more. To do this, the companies are working together to redesign hardware with AI specifically in mind, with a vision of expanding the use of AI to solve more problems in business and the world in general. This work includes developing new computing accelerators, technologies, and architectures designed and optimized specifically for AI computation. The AI Hardware Center has achieved several tapeouts and test chips of designs targeting advanced process manufacturing nodes, supporting its aggressive roadmap. Part of the roadmap to reach 1,000x performance improvement by 2029 was the delivery of AI processor cores that improve performance by 2.5x each year; IBM Research realized a gain of twice that in its first year. Synopsys' participation, which includes both technology and engineering personnel collaborating with the IBM researchers, focuses on addressing several of the key challenges in complex AI chip design, verification and manufacturing. Specifically, Synopsys brings expertise in three main areas: Multi-die integration in a package, silicon design and verification, with Synopsys3DIC Compiler, Fusion Design Platform™ and Verification Continuum® Platform, which include the use of functional verification, prototyping and emulation systems that address the size and scale of the designs being developed, and support for hardware and software co-design and co-analysis methodologies. Silicon engineering, provides software to address critical manufacturing and yield challenges introduced by process technologies such as the use of novel materials, gate-all-around 3D stacked architectures, and source and mask creation for EUV technology. Design Technology Co-Optimization (DTCO) solution combines capabilities to provide more options and help achieve global optimality. Silicon IP, which addresses the processing, memory performance and real-time connectivity requirements of AI chips, providing a broad portfolio of silicon-proven DesignWare® IP such as LPDDR5 and PCI Express® 5.0 for a wide array of applications.