Synopsys, Inc. announced that in collaboration with Samsung Foundry, more than 30 new interoperable process design kits (iPDKs) have been jointly developed, validated and support the Synopsys Custom Design Platform. These iPDKs provide broad coverage for Samsung Foundry's portfolio of advanced and legacy nodes. The Synopsys Custom Design Platform is a faster and more productive design and verification solution that delivers up to 5X faster layout and 2X faster design closure, providing maximum productivity to users of a wide range of Samsung Foundry process technologies. The Synopsys and Samsung collaborative effort included developing and validating a complete set of Samsung iPDKs, methodologies and design flows. Synopsys and Samsung also collaborated on implementing a comprehensive iPDK development and validation solution, based on Synopsys Custom Design Platform, that leverages the Custom Compiler™ design and layout environment. This environment includes HSPICE® circuit simulator, FineSim® circuit simulator, CustomSim™ FastSPICE circuit simulator, Custom WaveView™ waveform display, StarRC™ signoff extraction, and IC Validator physical verification. The broad library of over 30-plus Samsung and Synopsys iPDKs range from advanced gate-all-around or FinFET nodes including 3nm to 14nm, and many legacy nodes from 65nm to 130nm, enabling designers to access advanced features. The iPDKs enable designers to leverage analog and mixed-signal integrated circuits and IP using the latest Synopsys suite of custom implementation solutions. Each iPDK includes documentation and design infrastructure elements such as: simulation models for various devices, layer map and technology files, design rule check and layout versus schematic runset files for physical and electrical design rules verification, parasitic extraction deck, schematic symbol library, and parameterized cells, as well as power and performance optimizations used to help customers make the best chips.