XILINX, INC. November 26, 2021
Editor's Note: This content is republished from the MicroZed Chronicles, with permission from the author.
A few weeks ago, I wrote about migration from Spartan-6 devices to 7 Series devices. This originated from several client questions and inquiries about how this particular migration is best performed. This week, I am going to start looking at Spartan-6 migration more in depth, beginning with how to select the most appropriate device from the 7 Series range.
FPGA designs are complex and we need to consider each case individually. At a high level, however, we can guide the possible device selection from the flow chart below. This flow chart is based upon three key decisions points:
- MicroBlaze - If a MicroBlaze is used in the design, we need to determine if we want to continue using the MicroBlaze or migrate to a higher performing A9 or A53 in the Zynq or Zynq MPSoC. Migration from MicroBlaze to Arm processors cores is something we will look at in detail in another blog. However, the Xilinx Vitis framework and BSP generation does a lot of the heavy lifting for us.
- Transceivers Used - We need to determine if high speed multi-gigabit transceivers are being used as part of the application being migrated.
- Size of the Spartan-6 Device - We can fit the device in a Spartan-7 series device if the Spartan-6 device does not use transceivers and is a smaller device than the XCS6LX75. However, we need to consider a device from the Artix family if the Spartan-6 device for migration is larger.
Of course, these decision points are high-level decision points intended to guide potential device selection. Once the recommended family has been selected, the engineering performing the migration needs to carefully look through and consider additional salient points of the design and consider the following to identify the actual target migration device:
- Number of Block RAMS, DSP, clock management tiles, required.
- Maximum number of IO pins required along with the number of differential pins required.
- IO standards required - 7 Series IO is provided in two classes: High Range (HR) and High Performance. HR banks support IO standards of 3v3 and 2v5, while HP banks support IO standards up to 1v8 and are intended to support higher-performance interfaces. We also need to identify the specialist IO structures used in the Spartan-6 mitigation. Crucially ODELAY is only available within HP IO banks which means the engineer must consider selecting a device in the Kintex-7 range.
- Company supply chain preference - It might be sensible to select a slightly larger or different device as long as the design will migrate to align with company supply chain preferences to purchase common components which can be used across several projects within the company.
While migration from Spartan-6 to a 7 Series device comes with overheads, it also comes with opportunity. Depending upon the device selected for migration, a larger device or higher performance device could be selected. For example, a Kintex-7 part can be used in place of a Artix-7 or a MPSoC in place of a Zynq-7000 SoC. These selections provide the resources to support future product roadmap enhancements which may have previously been limited due to device utilization constraints. This is also the case when using a Zynq / MPSoC in place of a MicroBlaze processor. This provides easy support for a range of now commonly used interfaces such as USB and Gigabit Ethernet as well as advanced solutions such as SATA or DisplayPort. In an upcoming blog, we will look at the migration of the device itself now that we have selected the target component.
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Xilinx Inc. published this content on 26 November 2021 and is solely responsible for the information contained therein. Distributed by Public, unedited and unaltered, on 25 November 2021 00:09:03 UTC.
