The chipmaker joins several heavy hitters in the tech arena that have thrown their weight behind the project, including
The UCI-Express 1.0 spec defines a standard means for heterogeneous die-to-die communication. It's based on the Compute Express Link (CXL) protocol, which itself provides a common, cache-coherent interface for connecting CPUs, memory, accelerators, and other peripherals.
'This is an exciting opportunity to realize that vision someday of having multiple suppliers having dies in the same package and, for the customer, offering a much more robust solution than any one supplier can offer,'
UCI-Express effectively extends datacenter modularity down to the chip's internals. Instead of baking all of the functionality you need into a single die, chipmakers can mix and match functionality using chiplets from multiple vendors. You can think of it like Legos for chip packaging.
For example, if you're building a chip for an industrial environment that needs to process large quantities of visual data and then send it over the network, a chip could conceivably be assembled using a CPU from Intel, a GPU from
'That's the vision. When or if it will be achieved is a little unclear,' Durdan says. 'The vision is someday there could be a market for chiplets and multiple vendor's silicon all in one package, but I think that's going to take a little bit of time to develop.'
To be clear, chiplet architectures are by no means new.
It's a similar story with
'The thing, quite honestly, is that most of the designs that we've done that have multiple chips [were] a closed system. It was our chips talking to our chips,' Durdan says. 'The benefit we see to UCI-Express is just standardization. It's great that we have our own proprietary interface, but getting that other party to adopt our proprietary interface is a lot harder than getting that other party to adopt an industry-standard interface.'
With that said, Intel once Frankensteined an
In truth, the challenge isn't whether you can make chiplets work, that's already been solved for. Instead, the hard part is getting multiple vendors to agree on a standard way for how chiplets should talk to each other. And even this is addressed in part by CXL's broad support.
'We see the great value in aligning interconnect standards across the industry and look forward to contributing towards that goal as a member of the UCI-Express consortium,' Marvell CTO
It's not hard to imagine
'The challenge, quite frankly, is we've had a hard time narrowing in on a spec that's going to meet everyone's needs,' Durdan says.
In many ways,
With that said, it remains to be seen how chipmakers will implement this technology, let alone who decides which chips can and can't be packaged together.
(C) 2022 Electronic News Publishing, source