Netlist, Inc. announced that Mr. Charles Cargile, a director on the Board of Directors notified the Company of his resignation from the Board effective as of December 26, 2017. Concurrently with the effect of such resignation, Mr. Cargile will cease to serve in his other positions on the Board, including his position as Lead Independent Director on the Board and as a member of the Audit Committee and the Nominating and Corporate Governance Committee of the Board. The Board appointed Jun S. Cho as the Lead Independent Director on the Board and Jeffrey Benck as a member of the Audit Committee of the Board. Each of Mr. Cho and Mr. Benck currently serves as a director on the Board. Following the effect of the resignation of Mr. Cargile and the appointments of Mr. Cho and Mr. Benck to the new positions described above, the composition of the Board positions and committees are as follows: Chun K. Hong as Chairman of the Board. Lead Independent Director: Jun S. Cho. Audit Committee: Kiho Choi, Chair, Jeffrey Benck and Blake A. Welcher. Compensation Committee: Jun S. Cho, Chair and Kiho Choi. Nominating and Corporate Governance Committee: Blake A. Welcher, Chair and Jun S. Cho.
Netlist, Inc. provides memory solutions to enterprise customers in diverse industries. The Companyâs products, in various capacities and form factors, including its line of custom and specialty memory products, bring performance to customers in a variety of industries globally. It also licenses its intellectual property. The Companyâs commercially available memory subsystem products and other products that it sells include Component and Other Product Resales and Specialty DIMMs and Embedded Flash. Its portfolio of technologies and design techniques includes Distributed Buffer Architecture; Localized Module-Based Power Management Architecture; Proprietary PCB Designs; Thermal Management Designs; Compute Express Link Technology, and others. Its distributed buffer architecture enables the buffering of data signals using multiple data buffer devices distributed between a memory moduleâs edge connector and its installed dynamic random-access memory (DRAM).