Alphawave Semi announced the successful bring-up of its first chiplet-connectivity silicon platform on TSMC's most advanced 3nm process. This new silicon-proven Universal Chiplet Interconnect Express (UCIeTM) subsystem expands Alphawave Semi's portfolio and leadership in connectivity silicon. It paves the way for a robust, open chiplet ecosystem that accelerates connectivity and compute for high-performance AI systems. An industry-first live demo of Alphawave Semi's 24Gbps UCIe silicon platform on the TSMC 3nm process was recently unveiled at the Chiplet Summit in Santa Clara, CA.

Alphawave Semi?s 3nm UCIe complete PHY + Controller subsystem is capable of 24Gbps data rates, delivering high bandwidth density at extremely low power and low latency. The solution is compliant with the latest UCIe Revision 1.1 Specification and includes a highly configurable Die-to-Die D2D controller that supports streaming, PCIe®/CXLTM, AXI-4, AXI-S, CXS, and CHI protocols. The subsystem features Bit Error Rate (BER) Health Monitoring to ensure reliable operation.

The PHY can be configured to support TSMC?s advanced packaging technologies such as Chip-on-Wafer-on-Substrate (CoWoS®) and Integrated Fan-Out (InFO) which maximize signal densities, as well as organic substrates for a more cost-effective solution. Customers can benefit from Alphawave Semi?s application-optimized IP subsystems and advanced 2.5D/3D packaging expertise through the integration of advanced interfaces such as UCIe, PCIe, CXL, Multi-Standard-Serdes, and HBM onto custom chips and chiplets.