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MarketScreener Homepage  >  Equities  >  Tokyo  >  Renesas Electronics Corporation    6723   JP3164720009

RENESAS ELECTRONICS CORPORATION

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Japan - Patent Application Titled “Semiconductor Device, Load Drive System And Method Of Detecting Inductor Current” Published Online (USPTO 20190229717): Renesas Electronics Corporation

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08/14/2019 | 05:42pm EDT

2019 AUG 14 (NewsRx) -- By a News Reporter-Staff News Editor at Daily Asia Business -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventor TAJIMA, Hideyuki (Tokyo, Japan), filed on December 18, 2018, was made available online on July 25, 2019.

The assignee for this patent application is Renesas Electronics Corporation (Tokyo, Japan).

Reporters obtained the following quote from the background information supplied by the inventors: “Japanese Patent Application Laid-Open Publication No. 2011-97434 (Patent Document 1) discloses a current-controlled semiconductor device comprising a high-side MOSFET that is connected to a solenoid and is controlled by PWM, a current-voltage conversion circuit that detects a current flowing in the high-side MOSFET and converts the current into a voltage, and an AD converter that digitally converts the converted voltage.”

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventor’s summary information for this patent application: “Generally, in the field of power electronics, a system in which a switching element is controlled by PWM to perform feedback control of an inductor current flowing in an inductor is widely used. In such a system, it is necessary to detect the inductor current with using a method as disclosed in the Patent Document 1 and the like. At this time, in order to make the system perform controls with high accuracy, it is preferable that the inductor current is detected with high accuracy. However, as disclosed in, for example, the Patent Document 1, this configuration in which an output of a current-voltage conversion circuit is directly digitally converted would often cause a relatively large error in a detection value of the inductor current.

“The embodiments described below are provided in view of this situation, and other problems and novel features will be apparent from the description in the present specification with reference to the attached drawings.

“A semiconductor device according to one embodiment of the present invention includes a high-side transistor, a PWM signal-generating circuit, a monitor circuit, a current detection circuit, and a sample-and-hold circuit. The high-side transistor is coupled between a high-potential side power-supply potential and an output terminal and allows power to be accumulated in an inductor via the output terminal when the high-side transistor is controlled to be ON. The PWM signal-generating circuit generates a PWM signal that controls ON/OFF of the high-side transistor. The monitor circuit monitors a high-side control input potential applied to a control input node of the high-side transistor or monitors an output potential generated at the output terminal and generates either one or both of a high-side sampling timing and a high-side holding timing based on the monitored result. The current detection circuit detects an inductor current flowing in the inductor and generates a first detection voltage proportional to the detected current. The sample-and-hold circuit starts a sampling operation of the first detection voltage in response to the high-side sampling timing and starts a holding operation of the first detection voltage in response to the high-side holding timing so as to output a second detection voltage.

“According to the above-described embodiment, an inductor current can be detected with high accuracy.”

The claims supplied by the inventors are:

“1. A semiconductor device comprising: a high-side transistor coupled between a high-potential side power-supply potential and an output terminal, and allowing power to be accumulated in an inductor via the output terminal when the high-side transistor is controlled to be ON; a PWM signal-generating circuit generating a PWM signal that controls ON/OFF of the high-side transistor; a monitor circuit monitoring a high-side control input potential applied to a control input node of the high-side transistor or monitoring an output potential generated at the output terminal, and generating either one or both of a high-side sampling timing and a high-side holding timing based on the monitored result; a current detection circuit detecting an inductor current flowing in the inductor, and generating a first detection voltage proportional to the inductor current; and a sample-and-hold circuit starting a sampling operation of the first detection voltage in response to the high-side sampling timing, and starting a holding operation of the first detection voltage in response to the high-side holding timing so as to output a second detection voltage.

“2. The semiconductor device according to claim 1, wherein the monitor circuit generates the high-side sampling timing when the high-side control input potential or the output potential has risen to a determination potential which is a potential level in the vicinity of the high-potential side power-supply potential, and generates the high-side holding timing when the high-side control input potential or the output potential has fallen to the determination potential.

“3. The semiconductor device according to claim 2, wherein the monitor circuit comprises a clamp transistor, and the high-side control input potential or the output potential is applied to one end of the clamp transistor and a potential corresponding to the determination potential is applied to a control input node of the clamp transistor such that the clamp transistor clamps the high-side control input potential or the output potential at the determination potential serving as the lower limit value.

“4. The semiconductor device according to claim 1, wherein the monitor circuit further monitors a high-side ON/OFF control voltage which is a potential difference between the high-side control input potential and the output potential, generates the high-side sampling timing based on the monitored result of the high-side control input potential or the output potential, and generates the high-side holding timing based on the monitored result of the high-side ON/OFF control voltage.

“5. The semiconductor device according to claim 1, further comprising an analog-to-digital converter digitally converting the first detection voltage transmitted from the current detection circuit at a sampling frequency that is faster than a PWM frequency of the PWM signal, wherein the sample-and-hold circuit is constituted by a digital circuit that receives a digital signal from the analog-to-digital converter as an input.

“6. The semiconductor device according to claim 1, further comprising a delay circuit adding a delay to each of the high-side sampling timing and high-side holding timing transmitted from the monitor circuit, and outputting the result to the sample-and-hold circuit.

“7. The semiconductor device according to claim 1, further comprising a low-side transistor coupled between the output terminal and a low-potential side power-supply potential, having ON/OFF controlled complementarily with the high-side transistor, and allowing the inductor current to reflow when the low-side transistor is controlled to be ON, wherein the monitor circuit further monitors a low-side ON/OFF control voltage which is a potential difference between the low-potential side power-supply potential and a low-side control input potential applied to a control input node of the low-side transistor, and generates a low-side sampling timing and a low-side holding timing based on the monitored result, and the sample-and-hold circuit further starts a sampling operation of the first detection voltage in response to the low-side sampling timing, and starts a holding operation of the first detection voltage in response to the low-side holding timing.

“8. The semiconductor device according to claim 1, further comprising a compensator determining a PWM duty ratio such that an error between the second detection voltage transmitted from the sample-and-hold circuit and a predetermined target voltage is brought close to zero, and transmitting the PWM duty ratio to the PWM signal-generating circuit.

“9. A load drive system comprising: an inductor coupled to an output terminal and serving as a load; a high-side transistor coupled between a high-potential side power-supply potential and the output terminal, and allowing power to be accumulated in an inductor via the output terminal when the high-side transistor is controlled to be ON; a PWM signal-generating circuit generating a PWM signal that controls ON/OFF of the high-side transistor; a monitor circuit monitoring a high-side control input potential applied to a control input node of the high-side transistor or monitoring an output potential generated at the output terminal, and generating either one or both of a high-side sampling timing and a high-side holding timing based on the monitored result; a current detection circuit detecting an inductor current flowing in the inductor, and generating a first detection voltage proportional to the inductor current; and a sample-and-hold circuit starting a sampling operation of the first detection voltage in response to the high-side sampling timing, and starting a holding operation of the first detection voltage in response to the high-side holding timing so as to output a second detection voltage.

“10. The load drive system according to claim 9, wherein the monitor circuit generates the high-side sampling timing when the high-side control input potential or the output potential has risen to a determination potential which is a potential level in the vicinity of the high-potential side power-supply potential, and generates the high-side holding timing when the high-side control input potential or the output potential has fallen to the determination potential.

“11. The load drive system according to claim 9, wherein the monitor circuit further monitors a high-side ON/OFF control voltage which is a potential difference between the high-side control input potential and the output potential, generates the high-side sampling timing based on the monitored result of the high-side control input potential or the output potential, and generates the high-side holding timing based on the monitored result of the high-side ON/OFF control voltage.

“12. The load drive system according to claim 9, further comprising an analog-to-digital converter digitally converting the first detection voltage transmitted from the current detection circuit at a sampling frequency that is faster than a PWM frequency of the PWM signal, wherein the sample-and-hold circuit is constituted by a digital circuit that receives a digital signal from the analog-to-digital converter as an input.

“13. The load drive system according to claim 9, further comprising a low-side transistor coupled between the output terminal and a low-potential side power-supply potential, having ON/OFF controlled complementarily with the high-side transistor, and allowing the inductor current to reflow when the low-side transistor is controlled to be ON, wherein the monitor circuit further monitors a low-side ON/OFF control voltage which is a potential difference between the low-potential side power-supply potential and a low-side control input potential applied to a control input node of the low-side transistor, and generates a low-side sampling timing and a low-side holding timing based on the monitored result, and the sample-and-hold circuit further starts a sampling operation of the first detection voltage in response to the low-side sampling timing, and starts a holding operation of the first detection voltage in response to the low-side holding timing.

“14. The load drive system according to claim 9, further comprising a compensator determining a PWM duty ratio such that an error between the second detection voltage transmitted from the sample-and-hold circuit and a predetermined target voltage is brought close to zero, and transmitting the PWM duty ratio to the PWM signal-generating circuit.

“15. The load drive system according to claim 14, wherein the inductor is provided in a solenoid valve.

“16. The load drive system according to claim 9, wherein the high-side transistor, the PWM signal-generating circuit, the monitor circuit, the current detection circuit, and the sample-and-hold circuit are mounted on a single semiconductor chip.

“17. A method of detecting an inductor current by using a load drive system that includes: an inductor coupled to an output terminal and serving as a load; a high-side transistor coupled between a high-potential side power-supply potential and the output terminal, having ON/OFF controlled by a PWM signal, and allowing power to be accumulated in the inductor via the output terminal when the high-side transistor is controlled to be ON; and a current detection unit detecting an inductor current flowing in the inductor by sampling and holding operations, wherein the current detection unit performs: a first step of monitoring a high-side control input potential applied to a control input node of the high-side transistor or monitoring an output potential generated at the output terminal, a second step of generating either one or both of a high-side sampling timing and a high-side holding timing based on the monitored result obtained in the first step, and a third step of starting the sampling operation in response to the high-side sampling timing, and starting the holding operation in response to the high-side holding timing.

“18. The method of detecting an inductor current according to claim 17, wherein, in the second step, the current detection unit generates the high-side sampling timing when the high-side control input potential or the output potential has risen to a determination potential which is a potential level in the vicinity of the high-potential side power-supply potential, and generates the high-side holding timing when the high-side control input potential or the output potential has fallen to the determination potential.

“19. The method of detecting an inductor current according to claim 17, wherein, in the first step, the current detection unit further monitors a high-side ON/OFF control voltage which is a potential difference between the high-side control input potential and the output potential, and in the second step, the current detection unit generates the high-side sampling timing based on the monitored result of the high-side control input potential or the output potential, and generates the high-side holding timing based on the monitored result of the high-side ON/OFF control voltage.

“20. The method of detecting an inductor current according to claim 17, wherein the load drive system further comprises a low-side transistor coupled between the output terminal and a low-potential side power-supply potential, the low-side transistor having ON/OFF controlled complementarily with the high-side transistor and allowing the inductor current to reflow when the low-side transistor is controlled to be ON, in the first step, the current detection unit further monitors a low-side ON/OFF control voltage which is a potential difference between the low-potential side power-supply potential and a low-side control input potential applied to a control input node of the low-side transistor, in the second step, the current detection unit further generates a low-side sampling timing and a low-side holding timing based on the monitored result of the low-side ON/OFF control voltage, and in the third step, the current detection unit further starts the sampling operation in response to the low-side sampling timing, and starts the holding operation in response to the low-side holding timing.”

For more information, see this patent application: TAJIMA, Hideyuki. Semiconductor Device, Load Drive System And Method Of Detecting Inductor Current. Filed December 18, 2018 and posted July 25, 2019. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220190229717%22.PGNR.&OS=DN/20190229717&RS=DN/20190229717

(Our reports deliver fact-based news of research and discoveries from around the world.)

Copyright © 2019 NewsRx LLC, Daily Asia Business, source Geographic Newsletters

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Sales 2019 737 B
EBIT 2019 35 772 M
Net income 2019 18 455 M
Debt 2019 664 B
Yield 2019 -
P/E ratio 2019 55,9x
P/E ratio 2020 17,7x
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