GBT Technologies Inc. has been granted a fast track request by the United Stated Patent and Trademark Office for its nonprovisional patent application pertaining to the automatic correction of Integrated Circuits (IC) electrical connectivity mismatches. The patent application will undergo prioritized examination to accelerate the process. The original patent was filed on August 3, 2022 (application #17880055) to protect programmatic methodologies and algorithms to automate integrated circuits electrical connectivity mismatches correction, with the goal of shortening microchip's design cycle, particularly for advanced nanometer nodes of 5nm and below.

Layout Versus Schematic (LVS) checking process compares the IC's mask with the schematic netlist to determine if they match. The comparison results are considered 'pass' (or 'clean') if all the electronic devices and connectivity that are described in the schematic match the devices and connectivity in the layout. A 'fail' (or 'dirty') results means connectivity and/or devices mismatches.

Particularly with Analog or MIXED layout types, these mismatches would have to be fixed manually which is a tedious, time consuming, manual design work. A layout designer would have to debug the results, identifying the wrong electrical connections and/or device mismatches, and make the necessary layout modifications to achieve a 'clean' comparison. GBT's non-provisional patent application seeks to protect an algorithmic system and method to perform this process automatically.

With a click of a button, the system is designed to read the IC's schematic and layout data, compare the devices and electrical connectivity (wiring) and in case of mismatches detection, disconnect the faulty wires, and re- connect them in the layout to achieve a 'clean' LVS. The system is designed to automatically correct the layout, without causing any other LVS, geometrical (DRC), Reliability Verification (RV), and DFM (Design for Manufacturing) violations.