GBT Technologies Inc. filed a non-provisional patent application seeking to protect an Electronic Design Automation (EDA) software technology, internal code name Phi, which software is designed to automate the generation of reusable integrated circuits (IC) layout blocks. The concept produces a layout according to the IC's description and its goal is to save time during the design of a microchip. The intellectual property block can be used as a black-box to be inserted within existing or future IC projects, as a plug-and-play unit, with the goal of enabling time saving by avoiding entire re-design process.

The patent was filed on September 27, 2022 and received an application ID: 17953378. Intellectual Property (IP) as it pertains to semiconductors is a reusable logic or layout unit design that is developed with the intent of licensing to multiple vendors or using internally for using as building blocks in different chip designs. Using reusable IPs is an efficient method to quickly design a System on Chip (SoC).

A SoC is an IC that includes sub-units' components. It is typically consistent of core blocks for each to perform its own task such as internal storage, central processing unit (CPU), input/output ports and more. Modern SoCs also may include AI and other complex blocks to enable advanced capabilities.

Using reusable, pre-designed IP cores/blocks is becoming more and more crucial to minimize the entire IC's design time. The non-provisional patent application describes a system that has the goal of automatically generate IC layout IP blocks, reading a defined process design rules, constraints and the microchip's specifications. The goal of this IP is to reduce IC project's design and costs, as well as the silicon space occupied by large systems. GBT plans to continue its research and development efforts in this area of enabling efficient microchip's design projects and, in turn, reducing their time-to-market factor.