In its relentless pursuit of Moore's Law, Intel is unveiling key packaging, transistor and quantum physics breakthroughs fundamental to advancing and accelerating computing well into the next decade.
At IEEE International Electron Devices Meeting (IEDM) 2021, Intel outlined its path toward more than 10x interconnect density improvement in packaging with hybrid bonding, 30% to 50% area improvement in transistor scaling, major breakthroughs in new power and memory technologies, and new concepts in physics that may one day revolutionize computing.
'At Intel, the research and innovation necessary for advancing Moore's Law never stops. Our
Why It Matters: Moore's Law has been tracking innovations in computing that meet the demands of every technology generation from mainframes to mobile phones. This evolution is continuing today as we move into a new era of computing with unlimited data and artificial intelligence.
Continuous innovation is the cornerstone of Moore's Law. Intel's
How We Are Doing It: The breakthroughs revealed at IEDM 2021 demonstrate Intel is on track to continue the advancement and benefits of Moore's Law well beyond 2025 through its three areas of pathfinding.
Intel is pursuing significant research in essential scaling technologies for delivering more transistors in future product offerings: Researchers at the company have outlined solutions for the design, process, and assembly challenges of hybrid bonding interconnect, envisioning a more than 10x interconnect density improvement in packaging. At the Intel Accelerated event in July, Intel announced plans to introduce Foveros Direct, enabling sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking. To enable the ecosystem to gain benefits of advanced packaging, Intel is also calling for the establishment of new industry standards and testing procedures to enable a hybrid bonding chiplet ecosystem.
Looking beyond its gate-all-around RibbonFET, Intel is mastering the coming post-FinFET era with an approach to stacking multiple (CMOS) transistors that aims to achieve a maximized 30% to 50% logic scaling improvement for the continued advancement of Moore's Law by fitting more transistors per square millimeter.
Intel is also paving the way for Moore's Law advancement into the angstrom era with forward-looking research showing how novel materials just a few atoms thick can be used to make transistors that overcome the limitations of conventional silicon channels, enabling millions more transistors per die area for evermore powerful computing in the next decade.
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