Andes Technology Corporation announced that its AndesCore? A25 RISC-V CPU IP and AE350 peripheral subsystem is hardened and embedded in the GW5AST-138 FPGA chip from GOWIN Semiconductor. This integration, one of the first complete RISC-V microcontrollers in an FPGA, provides designers the A25 processor power and the peripherals most processors require without consuming any FPGA resources.

Thus, the hardware team can populate the FPGA with their value-added design while the software team can concurrently create application code based on the rich RISC-V ecosystem. The AndesCore? A25 hard core, running at 400MHz, supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications.

The AE350 AXI/AHB-based platform comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design. DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25's 32KByte I-Cache and D-Cache after cache misses. Off chip DDR3 provides data memory, SPI-Flash contains the A25's instruction memory (codes copied from SPI-Flash into DDR3 and Cache upon boot-up).  Besides hard instantiated functions, the GOWIN GW5AST-138 FPGA fabric affords 138K LUTs for custom design implementation.

 GOWIN EDA provides an easy-to-use FPGA hardware development environment for the Arora V.  The environment supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer. The GW5AST-138 FPGA with SDK with GOWIN_V1.9.9 Beta-3 will be available August 18, 2023 through distribution.