The full support of ZCC toolchain for AndeStar™ V5 Instruction Set Architecture will allow Andes and its silicon partners to achieve higher code density and performance for MCU and SoC products built on the V5 architecture. It opens the door to optimized RISC-V implementations across a wider range of applications.
The benchmark results demonstrate the ZCC toolchain's ability to optimize the system performance versus LLVM from AndeSight™ IDE. Based on AndesCore™ AX45 CPU, ZCC achieved a 6% boost over the baseline on CoreMark score, as well as an 18.9% performance improvement and 11.8% better code density on Embench-IoT (- O3). With -Os optimization, Embench-IoT attained a 10% code density gain and 9.1% faster performance.
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On the industry-standard SPECInt2006 benchmark, ZCC delivered a 30% lower dynamic instruction count compared to open-source LLVM 16.0 on a RV64GCBV RISC-V processor. It also achieved a 13% lower dynamic instruction count on a RV64GCB RISC-V processor.
These gains showcase the potential of the ZCC toolchain to help engineers maximize efficiency and real-world speedup across a wide variety of RISC-V implementations.
Benchmark results also highlight the powerful auto-vectorization capabilities of ZCC toolchain for AI chip development. ZCC achieved up to 91x higher performance versus open-source compilers on popular computing kernel functions. In some cases, the auto-vectorized output even matched or exceeded hand-optimized assemblies in both performance and efficiency.
These exceptional auto-vectorization results mean ZCC can substantially accelerate AI chip design and lower software maintenance costs. By reducing the need for time- consuming manual optimization of computational kernels, ZCC provides a streamlined path to deploying high-throughput AI accelerators
"Full support for AndeStar™ V5 ISA in the ZCC toolchain is just the starting point of our collaboration with Andes," said
"This collaboration between Terapines and Andes to optimize RISC-V processor performance and code density will greatly benefit our mutual customers," said Dr.
About Terapines:
Founded in late 2019, Terapines Technology specializes in developing RISC-V software/hardware co-design toolchain. With optimized compilers and simulators as core technologies, Terapines offers products and solutions across four key areas: software/hardware co-design and co-verification, functional safety checker, DSA and embedded development, and ROS operating systems. To learn more about Terapines' innovative RISC-V solutions, follow our WeChat official account or visit https://www.terapines.com.
About Andes :
Eighteen years in business and a Founding Premier member of
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Hsiao-Ling Lin Marcom Manager,Andes Technology Corp. hllin@andestech.com
Source:
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