Cadence Design Systems, Inc. announced that the Cadence® Pegasus™ Verification System is now qualified for the GlobalFoundries® (GF®) 12LP/12LP+ and 22FDX™ technologies. The collaboration with GF confirmed that the Pegasus Verification System meets the rigorous accuracy and runtime targets customers have come to expect with physical verification for these advanced GF nodes. GF-qualified rule decks are now available to help customers who are designing and taping out hyperscale, aerospace, 5G communications, consumer and automotive applications ramp up quickly.

The Pegasus Verification System offers several benefits to customers designing on GF 12LP/12LP+ and 22FDX technologies. Architected from the ground up to provide massively scalable runs, the Pegasus Verification System provides fast turnaround times and more predictable design cycle times with design rule checks (DRC), layout versus schematic (LVS), metal fill and design-for-manufacturing (DFM) . It features tight in-design integration with Cadence's Innovus™ Implementation System and Virtuoso® platform, providing improved productivity and checks throughout the implementation flow.

Also, designers can easily fulfill mandatory DFM requirements by leveraging integrated hotspot detection with seamless automated fixing. The Pegasus Verification System is part of the broader Cadence digital full flow, which provides optimal power, performance and area (PPA) with a faster path to design closure and supports Cadence's Intelligent System Design™ strategy, enabling SoC design excellence.